Research window: 2026-11-05 06:00 ~ 2026-11-06 06:00 (Beijing time, 24 hours; continuing from the cutoff of the previous daily report).

Sources: GitHub (full audit of 61 repos under org: flagos-ai, 123 commits within the window, 94 merged PRs, 255 updated open PRs within the window (87 of which were newly opened), pushes to 21 repos, atomic audit of Releases in 31 repos and Tags in 8 repos), Google News RSS (24 sets of Chinese and English query terms, via proxy), HN Algolia (8 sets), CSDN FlagOS column (per-article timestamp verification), BAAI Community (see the source list in the appendix for details).

Index for This Issue

  • Today’s highlights: Cambricon integrates fused attention forward and backward in Torch-FL, cutting CPU fallbacks in a Qwen3 training step from 190 to zero; the community submitted 7 FEPs (0163–0170) in a single day; Enflame clears 25 GCU300 rewrite tickets in one sweep, and FlagGems renames seven backend keys to versioned names (11-05)
  • I. Open-source project progress (GitHub activity)
    • 1.1 Organization cadence: pushes to 21 repos, 123 commits, 94 merged, 255 open (11-05)
    • 1.2 Community governance: 7 FEPs enter review within an hour, FlagMega v0.1 and TLE Raw five-backend registered (11-05)
    • 1.3 Release side: 2.3.0 records nvidia-cuda13.3, cuda12.8 frozen, torch upgraded to 2.13 (11-05)
    • 1.4 FlagGems: 25 of 33 merges belong to Enflame, seven backend keys renamed to versioned names (11-05)
    • 1.5 FlagTree: Hygon integrates TLE-Raw, ptxas resource usage enters compiler metadata (11-05)
    • 1.6 Torch-FL: Cambricon fused attention forward/backward completed, zero CPU fallbacks in training steps (11-05)
    • 1.7 FlagQuantum: 27 commits rearrange CI capacity, fault-tolerant compiler major branch enters integration (11-05)
    • 1.8 Vision and training side: FlagCV aligns with SGLang evaluation contract, FlagTrain integrates KMCompiler operators (11-05)
    • 1.9 Supporting infrastructure: docs model-list bot files tickets, optest and OpenCourse advance in small steps (11-05)
  • II. News coverage and ecosystem
    • 2.1 FlagOS 2.2 industry case: China Telecom cuts mHC training loss from 25% to 12% (11-05)
    • 2.2 Edge-side special: running large models on ARM CPU speeds up 21%–25%, multi-chip adaptation covers 35 chips (11-05)
    • 2.3 Channel verification: zero component-level hits, Enflame headline verified as an IPO retrospective piece (11-05)
  • III. Deep dive on member units and backend vendors
    • 3.1 Cambricon: CNNL fused attention forward and backward, 190 fallbacks cleared to zero (11-05)
    • 3.2 Enflame: GCU300 clears 25 tickets overnight, NVIDIA external symbols replaced one by one with local implementations (11-05)
    • 3.3 Hygon: HCU’s TLE-Raw and BF16 expert GEMM advance on two tracks (11-05)
    • 3.4 Ascend: Flash Attention fixes UB overflow, adds varlen forward and D=256 (11-05)
    • 3.5 Moore Threads, Iluvatar, MetaX, Kunlunxin, Tsingmicro and XuanTie: matrix multiplication and layout advance in batches (11-05)
  • IV. Summary and trend observations

I. Open-Source Project Progress (GitHub Activity)

1.1 Organization Rhythm: 21 Repos Pushed, 123 Commits, 94 Merges, 255 Under Review (11-05)

Date: 2026-11-05　Source: flagos-ai organization repositories · Commit search (within window) · Merged PR search (within window) · Open PR search (within window)

  • Totals: 21 of 61 repos had pushes within the window; 123 new commits on main branches, spread across 12 repos; 94 merged PRs from 14 repos and 32 authors.
  • Commit distribution: FlagGems 33, FlagQuantum 27, Torch-FL 12, build-infra 12 — 84 combined, or 68.3%; followed by FlagGems-sglang 8, FlagCV 8, FlagTrain 7.
  • Merge distribution: FlagGems 33, build-infra 12, Torch-FL 12 lead; then FlagTrain 7, FlagGems-sglang 6, FlagQuantum 5, FlagTree 5, FlagGems-vllm 5, FlagCV 4.
  • Per-person distribution: youseeyouonedayday 25 (all on the Enflame KernelGen line), lvyufeng 12 (Torch-FL), lukatao 9 (FlagCV, FlagGems-sglang, FlagTrain), tengqm 6 (build-infra), FlagQuantum bot 5, github-actions 5.
  • Under review: 255 updated within the window, of which 87 are newly opened; FlagGems 84 and FlagTree 71 together account for 155, or 60.8%.
  • Version surface: Release atom feeds for 31 repos and Tag atom feeds for 8 repos saw zero additions in the window; the most recent remains FlagCX v0.14.1 (11-01).
  • Versus previous period: commits 238→123, merges 167→94, pushed repos 26→21. Volume fell back to the normal range, yet 7 FEPs and a batch of release-engineering actions landed the same day — a “closing day” rather than a “volume day.”

1.2 Community Governance: 7 FEPs Enter Review Within an Hour, FlagMega v0.1 and TLE Raw Five-Backend Coverage Registered (11-05)

Date: 2026-11-05　Source: FEP-0163 · FEP-0164 · FEP-0165 · FEP-0166 · FEP-0167 · FEP-0168 · FEP-0170 · 2.3 release schedule

  • Action: Between 08:29 and 08:32 (Beijing time), six FEPs were opened within four minutes, and seven in total by 09:31. All were submitted by wbavon, each a single file of 104 to 207 lines, all marked Provisional Draft.
  • List: FEP-0163 FlagMega v0.1 (model compilation, vLLM integration, multi-card decoding), FEP-0164 TLE distributed fusion and auto-tuning, FEP-0165 TLE Raw covering five accelerator backends, FEP-0166 FLIR optimization for Ascend and GPGPU, FEP-0167 compiler optimization for twenty operator–device pairs, FEP-0168 FlagTree multi-platform support and Triton API compatibility, FEP-0170 FlagPrism v0.2 multi-backend debugging and profiling.
  • The most substantive: FEP-0163 maps five objectives to acceptance evidence — Qwen3.8 / GLM5.3 Flash model-to-MegaKernel compilation, BS=1 decoding, vLLM integration, tri-vendor support for NVIDIA / AMD / Iluvatar CoreX 5.0, and GLM5.3 Flash decode throughput more than 5% above vLLM on four H800 cards; it also explicitly notes that CoreX 5.0, the release matrix, and GLM checkpoint reproduction remain outstanding.
  • Common thread: All seven state that “no GPU or model acceptance has been run,” separating the scope declaration from the completion declaration. This is how a multi-backend capability matrix gets written as acceptance-testable items rather than a release checklist.
  • Timing: Per the 2.3 schedule, the FEP merge deadline is 11-13 and rc0 is 11-30. This batch appeared eight days before the deadline, squarely in the “scope-filling” window.
  • Same-batch branches: The community repo also had four codex/fep23-* branches pushed within the window, indicating FEP drafting and branch preparation run on the same pipeline.

1.3 Version Surface: 2.3.0 Records nvidia-cuda13.3, cuda12.8 Frozen, torch Bumped to 2.13 (11-05)

Date: 2026-11-05　Source: build-infra #1649 · build-infra #1652 · build-infra #1653 · build-infra #1654 · build-infra #1655 · build-infra #1647 · build-infra #1650

  • Version records: #1649 records 2.3.0 in the base docs and refreshes the image description; #1653 adds the 2.3.0 changelog date on the runtime side, targeting nvidia-cuda13.3. This is the first time the cuda13.3 line enters 2.3.0 coverage.
  • Upgrade contents: #1652 tracks cuda13.3 to torch 2.13 — torch 2.13.0+cu130, torchvision 0.28.0+cu130, triton 3.7.1; torchaudio stays at 2.11.0+cu130 and FlagTree stays at 0.7.0 (both decoupled from the torch version).
  • Freeze method: torch 2.13 no longer publishes cu128 wheels (that track ends at 2.11.0), so cuda12.8 cannot follow. The approach is to add an enabled: field to configs.yaml and set it to false — a freeze, not a deletion: specs, images, and docs all remain, with the image pinned to the flat tag of its last build.
  • Auditability: The script backend_enabled.py becomes the single resolver, shared by generate_matrix.py, the two status reports, and the flagcx and vllm-plugin registries, so “frozen” cannot enter any build matrix and no consumer can mistake a freeze for drift.
  • Related fixes: #1655 writes the flagcx rebuild triggered by torch-2.13 into the cuda13.3 dependency chain; #1654 provisions two LLVM trees for the flagtree HCU build and adds libzstd-dev.
  • Release pipeline: #1647 and #1650 record vllm wheel releases twice; #1346 removes the shared upload-nexus reusable workflow, consolidating the upload path.

1.4 FlagGems: 25 of 33 Merges Belong to Enflame, Seven Backend Keys Renamed to Versioned Form (11-05)

Date: 2026-11-05　Source: FlagGems #8446 · FlagGems #8287 · FlagGems #8028 · FlagGems #8393 · FlagGems #7581 · FlagGems #7246 · FlagGems #6706

  • Merge structure: Of the 33, 25 carry the KernelGen and Enflame prefixes (see 3.2), 3 are Kunlunxin, 2 Moore Threads, 1 Ascend, 1 Tsingmicro, and the rest are CI and general fixes.
  • Versioned backend keys: #8446 touches 12 files, +39/−38, changing seven bare vendor names in backends.yaml to version keys consistent with pyproject.toml — hygon-dtk2604, iluvatar-corex450, kunlunxin-xre5371, spacemit-xxx, sunrise-tangrt120, thead-ppu210, tsingmicro-tsm260610.
  • Why it matters: Under the old naming, uv pip install ".[tsingmicro]" would silently match no extra at all, installing neither torch nor flagtree, and setup.sh’s FlagTree check would throw ModuleNotFoundError: No module named 'torch' outright. With aligned key names, chip codenames and software-stack versions are written in one place for the first time, and installing the wrong version fails instead of being silently skipped.
  • Tsingmicro: #8287 updates the tsingmicro backend to 1103 — 190 files, +23195/−914, the largest single backend sync in this window.
  • Kunlunxin: #8028 optimizes four operator entry points above the dtype-equal-weight Gems Speedup threshold, with three-run cold-cache means of upsample_nearest2d 1.202, unique_consecutive 1.053, fake_quantize_per_tensor_affine 0.827, and foreach_clamp_max_scalar 0.967; #8393 adds XPU coverage including the cholesky solve helper.
  • Under review: 84 FlagGems PRs updated within the window (15 of them newly opened per the homepage stats), still the organization’s largest review pool.

1.5 FlagTree: Hygon Opens Up TLE-Raw, ptxas Resource Usage Enters Compiler Metadata (11-05)

Date: 2026-11-05　Source: FlagTree #1508 · FlagTree #1530 · FlagTree #1568 · FlagTree #1573 · FlagTree #1572 · FlagTree #1574 · FlagTree #1576

  • Merged: 5. #1508 adds the tle.raw path for Hygon HCU — 53 files, +5106/−17; #1530 parses register, spill, stack, and shared-memory usage from ptxas diagnostics; #1568 names the responsible owner in Feishu when CI fails; #1573 fixes the stderr redirection order in the vllm launch script.
  • HCU details: #1508 supports both eager and deferred modes and both HIP and MLIR sources (compiled to LLVM IR then embedded in Triton IR), and hooks into DUSHMEM streaming collective communication; it ships with three tutorials — ring shift, allgather GEMM, and GEMM allreduce. In the example, the HIP path for sort is 1.29× relative to torch.
  • Observability: #1530 writes resource usage into TLE compiler metadata, with the parser isolated from launch and communication behavior; repo-side aggregate verification shows all 154 TLE MLIR tests and 11 new C++ unit tests passing, and all 57 exact-fill, loop-pipelining, and scatter cases passing on H800.
  • Newly opened: 3. #1572 has Moore Threads preserve explicit blocked layouts during dot conversion; #1574 adds unroll bounds and hoisting prerequisite distances to reordered loop loads; #1576 enhances SoC-level dispatch for Enflame TLE.
  • Under review: 17 updated within the window, concentrated on TLE explicit layouts, Iluvatar native reproduction cases, and set_layout for FlagPrism / MetaX and PPU.

1.6 Torch-FL: Cambricon Fused Attention Forward/Backward Completed, Zero CPU Fallback in Training Step (11-05)

Date: 2026-11-05　Source: Torch-FL #748 · Torch-FL #749 · Torch-FL #757 · Torch-FL #754 · Torch-FL #745 · Torch-FL #756

  • Merged: 12, all submitted by lvyufeng, centered on operator consolidation for Cambricon MLU and opening up paths for Iluvatar.
  • Fused attention: #748 wires cnnlFlashAttentionForward_v2 into SDPA’s composite coverage, ending the history of “decomposing into three leaf operators” — at batch 2, 4 heads, sequence 4096, that B×H×S×S score matrix is about 256 MB, previously written to HBM and read back. #749 adds the backward pass with cnnlFlashAttentionBackward_v2, wrapping forward and backward together as a C++ autograd Function.
  • Fallback elimination: #757 first surveys a full Qwen3 causal language model training step and finds the residual 190 cpu_fallback calls come from just two operators — aten::mul.out 188 times and aten::embedding_dense_backward 2 times; after both are moved to execute on MLU via CNNL, the same step reports zero operator fallbacks. Registration is still produced by the code generator, so config and registration files cannot disagree.
  • Same-side fixes: #754 keeps Cambricon mul operands on device and shares the runtime queue; #750 and #755 fix argmax returning the axis length on slices containing NaN, and a graph-answer defect where no match marker was present.
  • Iluvatar side: #745 raises the Iluvatar operator cap so mul.Tensor can land on FlagGems; #746 records that the mean gap comes from the empty-reduction path.
  • CI: #756 keeps Kunlunxin’s 3.2 GB FlagTree wheel out of the pip cache; #760 restricts cache writes to push triggers only.
  • Under review: 6 updated within the window, including #752 synthesizing merged all-gather / reduce-scatter for inner backends lacking collective communication, #753 and #762 using ixblas axpy for Iluvatar’s add family, and #759’s MetaX DTensor and FSDP2 multi-card validation script.

1.7 FlagQuantum: 27 Commits Rework CI Capacity, Fault-Tolerant Compiler Branch Enters Integration (11-05)

Date: 2026-11-05　Source: FlagQuantum #1089 · FlagQuantum #1093 · FlagQuantum #1094 · FlagQuantum #1084 · FlagQuantum #1087 · FlagQuantum #1092

  • Merged: 5, three of them CI: #1089 decouples CPU capacity from the hosted queue and SDK downloads; #1093 pre-provisions the locked core environment and releases hosted capacity; #1094 pairs allocated CPU capacity with full coverage partitioning. The other two reorganize compiler modules by responsibility and add fault-tolerant test W1-B.
  • Main thread of the 27 commits: All around CI quality gates — qualifying image cache before migrating core suites, not skipping failure gates for superseded runs, rejecting cancelled dependencies on required merge gates, keeping live Qiskit dependency discovery on hosted runners, isolating the SDK queue, bounded retries for artifact uploads, spreading untimed large test modules into bounded batches, running core suites on a qualified offline A800 environment, reserving capacity for quality while balancing eight hosted slots, and cleaning up containers from cancelled jobs.
  • Fault-tolerant compiler branch: feat/ftqc-native-integration has about 20 commits in the window, porting QVR’s phase gradient, scaled addition, measurement adjoint, and Hamming-weight phase section by section; the main integration PR #1084 is open as a draft — 276 files, +31011/−92 — noting that subsequent modules will be filled in via separate commits before formal review is requested.
  • Error-correction work: #1087 wires in the Stim and PyMatching experimental workflow; #1092 supports matrix-defined weighted matching; #1085 adds tests for bounded W2/W3/W6 admission.
  • Assessment: None of the day’s 27 commits concerns quantum algorithms themselves; all are about making tests trustworthy and runners reproducible. For a project about to run fault-tolerant compilation, paying that bill first is reasonable.

1.8 Vision and Training Side: FlagCV Aligns with SGLang Evaluation Contract, FlagTrain Adds KMCompiler Operators (11-05)

Date: 2026-11-05　Source: FlagCV #4 · FlagCV #5 · FlagCV #6 · FlagCV #7 · FlagTrain #56 · FlagTrain #57 · FlagGems-vllm #1048 · FlagGems-sglang #294 · FlagSparse #117

  • FlagCV: 8 commits, 4 merges. Created only on 10-14, the repo is positioned as a computer vision operator library written in Triton, with interface shapes aligned to OpenCV and baselines compared against OpenCV CUDA. #5 adds a standalone OpenCV CUDA add reference adapter; #6 aligns add evaluation with FlagGems-sglang’s pytest contract (correctness records carrying candidate measured calls, dummy iteration reported separately, reference validation rejecting cases that bypass the candidate); #7 unifies device selection via GEMS_VENDOR.
  • FlagTrain: 7 merges, with the KMCompiler line continuing to add operators. #56 adds fused h_post bda forward and backward, measured at 1.190× and 1.702× on nvidia, 6.714× and 3.568× on PPU, 6.057× and 2.590× on MC550, and 7.087× and 3.500× on Iluvatar; #57 wires scaled_masked_softmax to Ascend, MetaX, Moore Threads, and Iluvatar simultaneously; #50 adds the quick_geglu Triton kernel; #54 unifies operator naming and test conventions.
  • FlagGems-vllm: 5 merges. #1048 implements fused_indexer_weight_scale with TLE on Ascend — two-stage pipeline, 4096-element tiling, UB allocation and copies via TLE, with shapes taken from real GLM-5.3-Flash calls; #1077, #1080, and #1085 fix three XCS marker issues in a row; #1071 makes setup.sh install FlagGems.
  • FlagGems-sglang: 8 commits, 6 merges. #294 unifies explicit device selection on GEMS_VENDOR, keeping DNN_VENDOR but emitting a FutureWarning and deferring to the new variable; #289 and #290 fix residual rounding and operator width on AMD gfx1100.
  • FlagSparse: #117 merged upstream from NCIC-AlphaSparse — 62 files, +4809/−280 — mainly finalizing q4 and 40 optimizations on MUSA.
  • vllm-plugin-FL: #698 syncs 0.4.0-dev forward into 0.5.0-dev, with the 0.5.0-dev branch pushed at 11-05 10:27; 20 under review.

1.9 Supporting Infrastructure: docs Model-List Bot Opens PR, optest and OpenCourse Advance in Small Steps (11-05)

Date: 2026-11-05　Source: docs #575 · optest #39 · OpenCourse #7 · FlagCX #694 · FlagBLAS #159

  • docs: At 19:01 the bot opened a ModelScope documentation update PR (#575), with the payload being that day’s model-list sync; #542, aihuanxin’s model-list PR, remains under review.
  • optest: No new commits on main within the window (the latest stops at the NV baseline script on 11-04 16:10); only the fix_workflow_1104 branch was pushed; #39, an image fix, is under review.
  • OpenCourse: #7 merges Harness Lab material updates, 2 commits.
  • FlagCX: #694 adds shared Net provider dispatch to DefaultBackend; #692’s PAL enabling PCI topology under AscendCL / DCMI fallback remains under review.
  • FlagBLAS: The new_ascend_gemm branch was pushed at 21:24; #159 optimizes Ascend cgemm and scores it against an archived H100 baseline, still under review.
  • Trident: A push occurred at 02:03 but with no new commits on main, corresponding to #4, the Monad intermediate-layer PR, updated at 02:03.

II. News Coverage and Ecosystem

2.1 FlagOS 2.2 Industry Case: China Telecom Cuts mHC Training Overhead from 25% to 12% (11-05)

Date: 2026-11-05　Source: CSDN FlagOS Column: No Compute Card Left Idle

  • Published: 11:23:59, titled “No Compute Card Left Idle: Industry Partners Build on FlagOS to Bring Diverse Compute into Real Workloads.” Figures cited are from the 2026 AI Open Computing Conference and Zhongzhi FlagOS Technical Conference.
  • A set of numbers for 2.2: Nine operator libraries totaling 1,454 operators; FlagTree covers 20 vendor chip backends in a single repo; 27.6% overall performance gain across 10 chips and over a thousand operators; Day0 adaptation of new models to 12 chips; 107 community members; 460,000 quarterly downloads, 4.76x the previous quarter.
  • China Telecom: Xingchen Xing4.0-29B-A4B (29B total parameters, 4B activated), open-sourced on September 17, was trained end-to-end on an Ascend 910C cluster, with precision alignment and deployment validation completed on 10 domestic chips on release day. The crux is the multi-channel residual operator mHC: NVIDIA’s official implementation is itself about 10% slower, the first Ascend version dropped 50%, and the team’s in-house version was stuck at 25%. After partnering with the FlagOS team to register FlagGems’ specialized optimized operator into the MindSpore + CANN + Ascend NPU training pipeline, cluster slowdown fell from 25% to 12%, and the adaptation has been open-sourced and merged into MindFormers.
  • Knock-on effects: Agent scenarios average 70K prompt length with a 200K maximum; after rewriting 12 long-sequence operators on FlagOS, first-token latency dropped 19.87% and decode speed rose by more than 20%. The hotline voice pre-processing pipeline aggregated and rewrote Spectrum-class operators, achieving a 10x speedup on three chips from Huawei, Moore Threads, and Iluvatar.
  • iSoftStone: Its Tianyuan intelligent computing platform bills by token, and GLM-5.2 generates a single token in 17.79 ms on four Ascend 910C servers, while the model provider’s published API admission threshold is 16.13 ms. After adopting FlagOS, it enabled PD disaggregation (Prefill and Decode each on two servers) with optimization on both sides, bringing latency within the admission threshold.
  • Other partners: Huixi Intelligent, Yixing Intelligent, and Pengfeng Technology also presented. The article’s conclusion: “Judging the maturity of domestic AI infrastructure is not about how many chips are supported, but whether a new model can run with deliverable throughput on release day by changing only configuration.”

2.2 Edge Session: ARM CPUs Run LLMs 21%–25% Faster, Multi-Chip Adaptation Covers 35 Chips (11-05)

Date: 2026-11-05　Source: CSDN FlagOS Column: From Cloud to Edge, the Last Mile of AI

  • Published: 14:10:28, an interview and livestream preview focused on edge AI, featuring Zhao Shuai, performance optimization engineer at Beijing Academy of Artificial Intelligence (BAAI).
  • Four highlights: Why edge AI can land now (smaller models, stronger compute, mature software); how edge, near-edge, and cloud should divide work, and the trade-offs between plugged-in and battery-powered devices; running MiniCPM and Qwen at hundreds of tokens/s on pure ARM CPUs without GPUs or NPUs, measured with SME2 and I8MM, for a 21%–25% performance gain; FlagOS multi-chip adaptation’s “optimize once, reuse across devices,” covering 21 chip vendors and 35 chips.
  • Scope difference: The 21 vendors / 35 chips here are edge and device-side adaptation counts, not the same dimension as the 107 community members and 12 Day0 chips announced at the conference in 2.2, and should not be conflated when cited.
  • Assessment: Treating edge separately signals that FlagOS’s narrative is expanding from “multi-chip on the cloud for training and inference” to “multi-chip on the device side.” This aligns with the repo-side direction of Torch-FL earlier adding the Apple Silicon MPS path.

2.3 Channel Check: Zero Component-Level Hits; Enflame Headline Verified as a Listing Retrospective (11-05)

Date: 2026-11-05　Source: Google News RSS · HN Algolia · BAAI Community

  • Google News: 24 Chinese and English queries returned 8 candidates in total within the 24-hour window. All seven component names (FlagOS, FlagGems, FlagScale, FlagTree, FlagPerf, FlagCX, KernelGen) had zero hits under Chinese queries, and BAAI FlagOS and flagos-ai also returned zero on the English side.
  • Member-term hits: Four came from “BAAI open source / chip” queries, consisting of paper explainers, event reports, and third-party model evaluations reposted by the BAAI Community, with no direct relation to FlagOS; one “Enflame Technology” headline, “Enflame Technology Debuts on A-Shares, Filling Out the STAR Market’s DSA Architecture Compute Map,” was verified to be a retrospective on Enflame’s September 11 STAR Market listing (688801), not a new event within the window, and the entire batch was discarded.
  • HN Algolia: FlagOS and FlagGems returned 8 and 3 broad matches respectively, with zero direct hits; BAAI’s 30 results likewise contained no FlagOS-related headlines.
  • BAAI Community: No new FlagOS posts within the window on the homepage or search page; the search page is still client-rendered and item lists cannot be scraped, so only the homepage check is authoritative.
  • Conclusion: On the news side, only the two new CSDN column articles were collectible for the day, with zero increment from other channels. This is consistent with the previous issue’s “zero component-level hits” conclusion and is the norm.

III. Deep Dive into Member Units and Backend Vendors

3.1 Cambricon: CNNL Fused Attention Forward and Backward, 190 Fallbacks Cleared to Zero (11-05)

Date: 2026-11-05　Source: Torch-FL #748 · Torch-FL #749 · Torch-FL #757 · Torch-FL #754

  • Root cause: SDPA was decomposed into three leaf operators on the Cambricon backend because cambricon was excluded from composite coverage, so every attention pass had to write the B×H×S×S score matrix into HBM and read it back. #748 restored CNNL’s fused forward into coverage: 8 files, +315/−27 lines.
  • Backward after forward: #749 filled in the gradient path with CNNL’s fused backward and wrapped it together with the forward into a C++ autograd Function, so a single training call runs both passes through the fused kernel. 3 files, +342/−112 lines.
  • Census-style wrap-up: #757 did not look at individual operators but first ran a fallback census over a complete Qwen3 causal language model training step, finding only two remaining fallback points—aten::mul.out at 188 times and aten::embedding_dense_backward at 2 times, 190 in total; after both were switched to execute via CNNL on MLU, the same step reported zero operator CPU fallbacks.
  • Engineering details: The Cambricon code generator was extended with these two operators, and gen_vendor_confs.py re-derived routing so that factory configuration and registration files can no longer contradict each other; #754 keeps mul’s operands on device and shares the runtime queue, avoiding round trips of intermediate results to the host.
  • Authors and tooling: All three PR bodies carry an AI agent information section, with tools dsh (DeepSeek Harness) and another coding agent, models labeled deepseek-v4.1-flash and gpt-6.1-sol, and human review uniformly by the same maintainer.
  • Assessment: Going from “it runs” to “zero fallbacks” is the dividing line for training usability. Of the 190 fallbacks, 188 came from a single operator, showing that this kind of wrap-up relies on a census rather than guesswork.

3.2 Enflame: GCU300 Clears 25 PRs Overnight, NVIDIA External Symbols Replaced One by One with Local Implementations (11-05)

Date: 2026-11-05　Source: FlagGems #8443 · FlagGems #8442 · FlagGems #8441 · FlagGems #8429 · FlagGems #8426 · FlagGems #8417 · FlagTree #1576

  • Scale: 25 merged PRs, all prefixed with KernelGen and Enflame, all by the same author; the 41 GCU300 coverage PRs newly opened in the previous issue began landing in bulk here.
  • Approach one: split out external symbols. Several PRs center on “runs without NVIDIA’s __nv_* external symbols”—__nv_nearbyintf, __nv_y0f / __nv_y1f, __nv_j0f, normcdfinv, etc., each replaced with a local implementation, corresponding to operators such as choose_qparams_optimized, special_bessel_y0/y1, special_bessel_j0, and special_ndtri.
  • Approach two: switch algorithm paths. special_chebyshev_polynomial_t now uses a dedicated kernel; linalg_householder_product uses a single-pass reflector sweep; linalg_inv_ex uses a single-kernel Gauss-Jordan; compute_linear_combination replaces the outer product with tl.dot; mixed_dtypes_linear rewrites packing and tiling.
  • Approach three: strip out incompatible compile-time features. renorm_’s autotuning causes this backend’s compiler to abort outright, so the whole block was dropped; the fake_quantize series switches to magic-add rounding to avoid extern dependencies; launch parameters for adaptive_avg_pool3d_backward, cholesky_inverse, and linalg_tensorinv are now planned on the host side.
  • Approach four: fix launch geometry. Launch geometry for special_i1e and special_modified_bessel_k0 was corrected one by one, along with the batch-norm functional kernel geometry for linalg_householder_product.
  • Compiler side: #1576 newly opened, adding SoC-level distribution enhancements for TLE, moving operator-level rewrites one step toward compiler capabilities.
  • Assessment: The method on this line is to translate “upstream formulations” into “formulations this backend supports,” clearing the ledger item by item. The cost is a large number of PRs with small individual changes; the benefit is that coverage can go from a few dozen operators to over a thousand within two weeks.

3.3 Hygon: HCU’s TLE-Raw and BF16 Expert GEMM Advance on Two Tracks (11-05)

Date: 2026-11-05　Source: FlagTree #1508 · build-infra #1654 · TransformerEngine-FL #153 · FlagAttention #123 · FlagGems #8446

  • Compiler side: #1508 adds tle.raw support for HCU, 53 files, +5106 lines; it supports both HIP and MLIR sources, both eager and deferred modes, and integrates DUSHMEM streaming collective communication, with three accompanying tutorials (ring shift, allgather GEMM, GEMM allreduce).
  • Build side: #1654 lays out two LLVM trees in build-infra for flagtree’s HCU build and adds libzstd-dev, indicating that HCU’s LLVM version has not yet converged to a single tree.
  • Training side: TransformerEngine-FL #153 newly opened, adding an optional BF16 expert GEMM path for Qwen3.5-35B (opt-in, no change to default behavior).
  • Attention side: FlagAttention #123’s AttnRes backend is still under review, a new operator direction for Hygon attention.
  • Naming: FlagGems #8446 sets Hygon’s backend key to hygon-dtk2604, tied to DTK 26.04; the 2.3.0 coverage noted in the previous issue also includes a DTK 26.10 line.
  • Assessment: Hygon’s two actions that day operate at different layers—TLE-Raw opens the compiler to vendor hand-written kernels, while BF16 expert GEMM pushes training performance down. The former is a large one-time investment; the latter directly targets the model.

3.4 Ascend: Flash Attention Fixes UB Overflow, Adds varlen Forward and D=256 (11-05)

Date: 2026-11-05　Source: FlagGems #7581 · FlagGems-vllm #1048 · FlagGems-vllm #1077 · FlagBLAS #159 · FlagCX #692 · FlagTree #1507

  • Flash Attention: #7581 fixes UB overflow and backward compilation issues in forward and backward, 5 files, +1865/−286 lines. The approach bounds both tiling and buffering for forward and backward, compiles dQ separately from dK/dV while retaining FP32 accumulation, tail handling, and GQA gradient reduction.
  • Two capabilities added: Ascend’s varlen forward is newly added and registered; for dense D=256, K is first loaded in contiguous [N, D] order and then transposed for QK, the forward KV tile is enlarged, and only dQ’s query tile is enlarged, while dK/dV stays within the buffer limit.
  • Boundary alignment: The causal full mask and masked region are aligned to KV tile boundaries, avoiding tile overlap when BLOCK_N is greater than BLOCK_M.
  • Regression: Forward regression against a CPU reference was added, covering FP16 and BF16, causal and non-causal, padded head dimensions, sequence tails, and GQA.
  • Inference side: #1048 implements a fused indexer weight scaling operator with TLE, two-stage pipeline, 4096-element tiling, UB allocation via TLE, retaining FP32 output; shapes taken from GLM-5.3-Flash. Three XCS tag fixes the same day aligned perf inputs with tags.
  • Other: #159 optimizes Ascend cgemm and scores it against an archived H100 baseline (under review); #692 enables PCI topology for PAL under AscendCL and DCMI fallback (under review); #1507 makes the Ascend 3.5 compiler export triton_key (under review).

3.5 Moore Threads, Iluvatar, MetaX, Kunlunxin, Tsingmicro, and XuanTie: Matrix Multiplication and Layouts Advance in Batches (11-05)

Date: 2026-11-05　Source: FlagGems #7246 · FlagGems #6706 · FlagGems #8028 · FlagGems #8287 · Torch-FL #745 · FlagAttention #127 · FlagAttention #119

  • Moore Threads: #7246 rewrites mm on MP31, single file +2472/−146 lines—selecting among GEMV, split-K, TME/SQMMA pipeline, and persistent paths by dtype, size, and NN/NT layout; FP32 goes to a vector-times-matrix dedicated path, TF32x3 tiled GEMM, and split-K, while FP16/BF16 go to warp specialization with TME transfers plus SQMMA compute, using TMECachePolicy for cache residency hints. #6706 adds shape-aware TLE/SQMMA implementations for bmm and bmm.out (9 files, +2369 lines), requiring the matching FlagTree segmented SPMC pipeline v2. #1572 on the FlagTree side makes dot conversion preserve explicit blocked layouts.
  • Iluvatar: #745 lifts Iluvatar’s operator cap so that mul.Tensor can land in FlagGems; #753 and #762 are under review, unifying the add family under ixblas axpy; on the CI side, FlagScale #1322 and Megatron-LM-FL #213 are both adding Iluvatar pipelines.
  • MetaX: #57’s scaled_masked_softmax covers MetaX; on the FlagGems side, #8414’s layernorm, #6811’s C550 matrix multiplication, and #6807’s addmm/router GEMM are still under review; FlagTree #1496 adds minimal MetaX integration to FlagPrism, and #1471 adds CommonIR set_layout and layout autotuning; FlagAttention #119 adds Parallax’s prefill and decode.
  • Kunlunxin: #8028 brings four operators above the 0.8 Gems Speedup threshold, and #8393 adds XPU coverage including the cholesky solve helper; Torch-FL #756 keeps the 3.2 GB FlagTree wheel out of the pip cache.
  • Tsingmicro: #8287 updates the backend to 1103, 190 files, +23195/−914 lines, the largest single backend sync of the day; the backend key is set to tsingmicro-tsm260610.
  • XuanTie: FlagAttention #127 newly opened, adding and optimizing Wall Attention for PPU-ZW810E; FlagGems #8446 sets the backend key to thead-ppu210; #8489 newly opened, fixing and optimizing convolution_backward across Ascend, Moore Threads, and XuanTie.
  • Horizon: No commits in this window; its BPU line had just completed chained execution and operator library fixes in the previous issue (11-04), with nothing new this issue.

IV. Summary and Trend Observations

Date: 2026-11-05 ~ 2026-11-06　Source: flagos-ai organization · PR links for each item in this issue (see appendix)

  • In one sentence: The day’s main thread was “closing out”—Enflame cleared 25 GCU300 rewrite PRs in one pass, Cambricon completed fused attention forward and backward and drove training-step fallbacks to zero, and the community sent 7 FEPs into review, preparing for 2.3’s 11-13 deadline.
  • Observation one: The pace fell back, but the direction became clearer. Commits went 238→123 and merges 167→94, but what landed in specific repos was all “finishing the last stretch”: Torch-FL adding backward, FlagGems clearing the ledger, FlagTree opening the door to vendor hand-written kernels. On a wrap-up day after the breadth phase ends, output looks smaller, but the push toward usability is more direct.
  • Observation two: The FEP batch is the real boundary of 2.3’s scope. The seven new FEPs point to the same thing—writing “multi-backend capability” as acceptance-testable items: FlagMega v0.1’s MegaKernel compilation, TLE Raw’s five backends, FlagPrism v0.2’s multi-backend debugging, and FLIR optimization on Ascend and GPGPU. All are Provisional Drafts and all note that GPU acceptance has not been run, indicating these are scope declarations rather than completion declarations; the real hard boundary is the 11-13 merge deadline.
  • Observation three: Version engineering is beginning to “retire audibly”. cuda12.8 was frozen because torch 2.13 no longer ships cu128 wheels; the approach is to add an enabled field and set it to false, keeping specs and docs while letting the sole resolver block it from all matrices. Freezing is neither deletion nor laissez-faire—this pattern is worth reusing for other backend retirements.
  • Observation four: CI capacity became FlagQuantum’s main work. None of the 27 commits involved quantum algorithms; all were about sorting out hosted runner capacity, image eligibility, coverage partitioning, and cancellation semantics. The fault-tolerant compilation branch already has an integration PR of 276 files and 31k lines; if test infrastructure can’t keep up, it’s just spinning in place.
  • Observation five: AI agents are the main committers; the bottleneck is review. Of the 94 merges, 25 came from the same agent session, with PR bodies carrying tool, model, and human-review fields. The review-side pending pool still has 255 PRs, with 87 newly opened, and FlagGems and FlagTree account for 60%—writing is no longer the bottleneck.
  • To watch: Whether the seven FEPs can be taken in before 11-13; whether FlagGems’ pending pool will drop along with Enflame’s clearing; when FlagQuantum’s fault-tolerant compilation integration PR will move from draft to formal review; and whether the cuda13.3 line will touch the torch version again before 2.3.0 rc0 (11-30).

Appendix: Source Verification Table and Full Source List

Source Verification Table

Source Verification Result
flagos-ai organization repositories (61 repos) 21 repos pushed within the window; new commits on main branches concentrated in four repos: FlagGems, FlagQuantum, Torch-FL, build-infra
Commit search (committer-date window) 123 hits across 12 repos; FlagGems 33 and FlagQuantum 27 account for 48.8%
Merged PR search (merged window) 94 hits from 14 repos and 32 authors; FlagGems 33, build-infra 12, Torch-FL 12 rank top three
Open PR search (updated window) 255 hits, of which 87 newly opened; FlagGems 84 and FlagTree 71 account for 60.8%
Release / Tag atomic check (31 repos + 8 repos) Zero new releases within the window; the most recent remains FlagCX v0.14.1 (11-01)
Google News RSS (24 Chinese and English queries) All seven component-name groups returned zero hits; 8 member-word candidates verified as community reposts, event write-ups, and IPO retrospective pieces, all removed
HN Algolia (8 queries) FlagOS 8 and FlagGems 3 loose matches; zero direct hits
CSDN FlagOS column Homepage 15 articles checked one by one: 2 new articles fall within the window (11-05 11:23 and 14:10), the rest are old articles from August to October
BAAI Hub Search page is client-rendered and cannot be scraped; no new FlagOS-related posts on the homepage within the window
2.3 release checklist (community release/2.3) Directory contains only the release schedule; the checklist file will be generated at feature freeze on 11-30 as planned

Full Source List