Reporting period: Monday, September 14, 2026 to Sunday, September 20, 2026, 7 calendar days in total Sources: This publication’s daily FlagOS activity reports (five weekday issues: 09-14, 09-15, 09-16, 09-17, 09-18, plus a weekend supplementary issue on 09-20, 6 issues in total); all items come from verified sources for the respective period Editorial note: This period covers four dimensions: release governance (2.2 RC cadence and GA scheduling), component and code co-development, member organizations and vendor adaptation, and ecosystem and community; across the five daily report windows there were approximately 720 commits in total, covering nearly 30 repositories within the org, and all technical facts come from hands-on verification of code repositories and official release materials

1. Weekly Highlights

  • FlagOS 2.2 RC2 full-stack synchronized tagging, the second release-candidate snapshot of the full cycle (09-14): At 10:35 on 09-14, the community repository merged the 2.2 RC2 manifest (release-2.2-rc2.yaml, adding 251 lines); then within ten minutes from 10:45 to 10:54, 23 component repositories successively tagged rc2.post1 or published Releases, with 26 tagging actions recorded across the day covering 22 repositories, and FlagTree’s three Triton variants plus one xpu3.6 tag completed the same day. The first Releases with release notes were FlagGems v5.4.0 and FlagSparse v0.3.0 (both rc2.post1).
  • build-infra version field raised to 2.2.0, all 20 backend images rebuilt in batch (09-17 ~ 09-20): PR #916 at 08:49 on 09-17 raised the version in configs.yaml from 2.1.2 to 2.2.0 and switched flaggems from 5.3.5 to 5.4.0-rc2.post2 — the only global switch within the org before 2.2 GA; from 09-19 to 09-20, all 20 backend vLLM images were authorized for batch rebuild with 2.2.0 / plugin post2 and written back one by one, making it the largest engineering action of the week.
  • community merged 20 FEPs in one batch, finalizing the 2.2 feature list and release boundaries (09-17): Numbered 0081 to 0100, spanning operators, compilers, frameworks, training, networking, edge, and AI for science; each includes a “release boundaries and evidence” section, and the same batch contains both proof-of-concept items marked as implemented (FEP-0095 Common IR) and capability items deliberately left in draft (FEP-0100 KernelGen) — not treating the roadmap as delivery.
  • Torch-FL’s six platforms shift to FlagGems-first, with the dispatch layer becoming the main battleground (09-15/09-16): The PPU routing table expanded from 11 entries to 478 and was finalized at 435; of the 482 operators covered by FlagGems, 47 remain on vendor kernels and are individually named; CUDA, DCU, GCU, Ascend, and MUSA adjusted in the same direction. This is the first complete quantification at the dispatch layer of the proposition “one operator library reused across chips.”
  • Open3D-PIMC goes from open-source announcement to code landing (09-14 ~ 09-16): About 44 hours after the open-source announcement at the China Computing Conference, the repository received its first root commit, bringing in 662 entries at once (the raisa-inductor compilation layer and the rcs2 C++ runtime), as the programming model and compilation stack for 3D computing chips entered engineering status.
  • Release engineering fully converging: artifacts, packaging, and gating proceed in parallel (09-15 ~ 09-20): The Ascend FlagTree wheel upload path worked end-to-end for the first time (flagtree-0.7.0rc2+ascend3.5 and others reached the artifact repository); FlagTree’s DEB packaging and Nexus publishing were merged into the shared workflow; plugin wheels switched to “build once, distribute indexes across all vendors”; images began self-reporting plugin versions and annotating the compilation base one by one; FlagQuantum’s coverage floor was raised to 75%.
  • The ecosystem enters conference and competition season (09-18 ~ 09-21): Registration opened for the 2026 AI Open Computing Conference and the Zhongzhi FlagOS Technology Conference (October 17–18, Beijing); submissions opened on 09-21 for the inference throughput optimization challenge co-hosted by FlagOS and MiniCPM; outputs from the SGLang cross-chip operator optimization competition continue to enter the main repository as PRs.
  • Industry: member companies see a dense cluster of capital and financing events (09-15 ~ 09-17): Post-IPO commentary on Enflame continued to build (the public figures of a 179.22% first-day gain and a market value of RMB 170.85 billion were repeatedly cited); D-Robotics completed a USD 400 million Series C (led by Mirae Asset); MetaX surged 14.44% on 09-17 amid reports of reductions by several institutions — the capital market’s focus continues to shift from “can it be built” to scaled delivery and profit realization.

II. Versions and Release Activity

RC Cadence and GA Milestones

  • 2.2 Timeline: Feature freeze 08-31, testing and stabilization period 09-01 to 09-24, GA scheduled for 2026-09-28; as of the 09-17 audit, all 7 issues under the “FlagOS 2.2” milestone remain open, with the same due date of 09-28; the graduation criterion is that “an executable test plan passes during the test period,” after which the FEP status moves from implementable to implemented; security patches and critical defects go through an expedited channel requiring TSC approval.
  • RC1 to RC2: RC1 was the product of the previous cycle’s end and was still in the rc1.postN iteration slot early this week (FlagGems at rc1.post2); the RC2 manifest was generated on 09-14 at 10:35, covering 24 module entries across five groups—infrastructure, operators, inference plugins, training, and release & tooling—with the rule that “versions stay consistent with rc0/rc1, advancing only in the .postN iteration slot.”
  • Three RC2 iterations: FlagGems went from rc2.post1 (09-14) through rc2.post2 (09-15 11:21, community #110, driven by two fixes: Triton 3.5 compatibility for flash_attention_backward and tl.map_elementwise gating) to rc2.post3 (recorded 09-18); FlagCX advanced to rc2.post2; the remaining entries stayed at rc2.post1.
  • Branch and tagging automation: From 09-17 23:29 to 23:33, ten module repositories simultaneously cut rc2 integration branches and were tagged (verified via full git ls-remote refs), executed in batch by the release-branch-tag workflow calling manage-release.py per the manifest; the community-side 2.2 project sync workflow runs every 15 minutes, with release status now derived from linked PRs.
  • GA countdown: Narrowed from 14 days on the first day of the window (09-14) to 8 days at the window’s end (09-20), with the test period entering its latter half of “bug fixes only.”

Component Tags and Release Manifest (Within the Window)

  • FlagGems: v5.4.0-rc2.post1 (09-14, Release) to v5.4.0-rc2.post2 (09-15) to rc2.post3 (recorded 09-18); the stable line remains v5.3.6 (around 09-11).
  • FlagSparse: v0.3.0-rc2.post1 (09-14, Release with release notes).
  • FlagCX: v0.14.0-rc2.post1 (09-14) to rc2.post2 (verified 09-17/18).
  • FlagTree: 0.7.0rc2.post1 across the Triton 3.6 / 3.5 / 3.3 lines and 0.7.0rc2+xpu3.6 (09-14); on 09-17, backend tags for 0.7.0rc2 including metax, mthreads, enflame, and tsingmicro were added; on 09-18, the Kunlunxin xpu line iterated further to 0.7.0rc3+xpu3.6 (tags verified).
  • FlagAttention: v0.4.0-rc2.post1.
  • Other components (tagged in a batch on 09-14, rc2.post1): FlagFFT v0.2.0, FlagDNN / FlagTensor / FlagAudio / FlagBLAS v0.3.0, FlagGems-vllm v0.2.0, FlagGems-sglang v0.1.0, Torch-FL v0.2.0, sglang-plugin-FL v0.2.0, TransformerEngine-FL / Megatron-LM-FL v0.3.0, FlagOS-Compressor v0.1.0, KernelGen v2.2.0, KernelGenBench v0.2.0, FlagRelease v0.3.0; FlagScale is at v2.1.0-rc2.post1 (having moved off the 2.0 line); vllm-plugin-FL follows two version lines, 0.3.0 and 0.2.2.

Image and Artifact Status

  • All 20 backends rebuilt: After the authorization commit (#938) was issued on 09-20 at 03:07, the bot account recorded new image tags backend by backend within just over an hour; the recorded 2.2.0-0.3.0rc2.post2 tier covers Ascend (cann8.5.0, cann9.0.0, and 910c variants), Cambricon (neuware4.4.3 / 4.7.2), Moore Threads (musa4.3.6 / 5.2.0), Enflame (tops1.9.10 / 1.10.6), MetaX (maca3.7.2.1 / 3.8.1.3), Hygon (dtk26.04), Iluvatar (corex4.5.0), Kunlunxin (xre5.37.1), Infinigence (tangrt1.2.0), and NVIDIA (cuda12.8 / 13.3); a separate batch of the plugin version line 0.2.2rc2.post2 landed earlier.
  • Distribution channel consolidation: Plugin wheels now build once and publish to all vendor indexes (#934), version numbers are derived from git refs (#932), runtime dependencies are fetched from vendor indexes (#930), and the Ascend line adds the cann-shmem package (#939).
  • Three verifiability items: Images self-report the actually installed plugin version (#937), images never built are explicitly marked TBD in the docs (#948), and each image is annotated with the actually compiled FlagTree base (#953); the status matrix’s statistical criteria are also pinned down (#932/#933).
  • Version pinning rollback and compatibility handling: On 09-20, NVIDIA cuda13.3 (#940) and the two MetaX MACA backends (#943) were pinned back to FlagTree 0.6.1, and Enflame tops1.9.10 was pinned back to 0.6.0 (#944); in tandem, the FlagTune cost model was disabled per the pinned state (#947)—forming a complete “rollback + adaptation” set with the version bumps earlier in the week.
  • Ascend and release artifacts: The FlagTree wheel upload channel worked end-to-end for the first time (flagtree-0.7.0rc2+ascend3.5 and flagtree-0.6.0+ascend3.2 reached the artifact repository, with build times of 26 / 14 minutes); the build-infra repository’s own tag remains at v2.1.1, and the v2.2.0 tag has not yet landed within the window.

III. Components and Code Co-building

This week, the org’s five window periods recorded 98 / 119 / 150 / 147 / 206 commits, totaling approximately 720 (the 09-17 and 09-18 windows overlap by about 1.4 hours, with a small amount of double-counting). The following is aggregated by module.

Operators and Domain Libraries (FlagGems and various domain libraries)

  • FlagGems (mainline, the first line this week): Five window periods recorded 12 / 43 / 71 / 40 / 38 commits, totaling approximately 200. Three production lines run in parallel: KernelGen batch ingestion (injecting 50+ Nvidia operators in one week, covering four categories—linear algebra, special functions, training backward, and pooling/sampling—with representative entries including nanquantile, logdet, linalg_polar, GRU and LSTM backward kernels, Lanczos upsampling backward, fused_adagrad, fused_sgd); KMCompiler operator-by-operator completion (Ascend matrix_rank, igammac, gru, adaptive_max_pool3d, linalg_solve_triangular; Hygon and MetaX share the linalg_lstsq multi-backend implementation); Kunlunxin TLE refactoring (sum / sum_dim migrated to tle.gpu, plus a batch of roughly ten backend fixes: persistent kernel for grouped_mm with large M and small K, SDPA attention, mse_loss full-block masking, etc.).
  • Quantization mainline: Hygon W8A8 INT8 GEMM (#6185, long-K reduction overflow protection) and TLE enablement (#6247); Moore Threads W8A16 FP8 RMSNorm (#6210) and native FP8 W8A8 matmul (#6211); MetaX W8A16 RMSNorm (#6326); FP8 topk routing (#4412). Quantization coverage is spreading from the matmul layer to normalization and adjacent operators.
  • Backend fixes and expansion: Hygon DCU FlashAttention forward/backward fix (#5822), fused rrelu backend kernel (#6379); DAMO XuanTie PPU backend enables TLE (#6423); MetaX masked_fill out-of-bounds and invalid-config fix (#6480); Ascend dedicated linear operators (#6456), swiglu and grouped_matmul (#6324 / #6325), Top-K (#6354); Kunlunxin FlagTree dependency bumped to 0.6.1+xpu3.6 (#6393), proactive rollback of the tle.raw scalar comparison fast path (#6409), fixes for five operators: masked_fill / sinh / mish / hardswish / index_fill (#6328).
  • Engineering quality: Fixed the 16×16 hang in linalg_svd (#6301), dtype mismatch in addmv scalar bias (#6149), nansum integer dtype (#6351); completed init.py for seven backend subpackages; operator export checks, KernelGen test markers now scan only added lines, benchmark pytest markers aligned with operator registration (#6489); AMD W7900D enters the weekly test matrix (#6312).
  • FlagGems-Experimental (experimental ground): Hygon batch-ingested 17 operators within one hour (including special functions, linear algebra, numerical and indexing categories, plus a _scaled fix); Moore Threads added cholesky_inverse, linalg_ldl_solve, ormqr, etc.; Kunlunxin added mvlgamma; 09-17 fixed MetaX index_select (#419), added conv_depthwise2d (#391) and dense_dim (#639); 09-20 landed ten more small Nvidia operators (sparse and view categories, a precursor step for ferrying from the experimental ground to the mainline).
  • FlagSparse: Introduced an external collaboration branch (NCIC-AlphaSparse) via a merge commit, and advanced MUSA, MACA, and DCU backend adaptation with 39 commits (including separation of spgemm single/double precision tests, addition of a C wrapper layer, with one batch rollback followed by re-convergence).
  • FlagFFT: 36 FFT operators moved to acceptance state in one shot (+2151/-2298, with independent NumPy verification and runtime plans), after which acceptance coverage was made mandatory; 09-17 left 3D transpose verification records for MUSA and MACA respectively and unified the Triton JIT runtime dependency pinning; the acceptance framework was continuously refactored in the final stretch of the window (pipeline flow, log adjudication, on-demand regeneration).
  • FlagDNN: Reorganized the implementation architecture for the Iluvatar and Hygon platforms, added a text sum operator, and converged the test surface across four platforms (PPU / Moore Threads / Ascend / Iluvatar).
  • FlagBLAS and FlagAudio: FlagBLAS fixed the packaging configuration for the DAMO XuanTie backend; FlagAudio merged its first three PRs (spectrogram Triton operator, gain identity check and lazy import, packaging wrap-up), all from external contributor branches, plus a CI upload path.

Compilers and Communication Libraries (FlagTree and FlagCX)

  • FlagTree: Three release engineering items (DEB packaging matrix adds ubuntu22.04 / python3.12, release packages switched to a shared workflow pushing to Nexus, stripped debug info from libtriton and libproton), with the packaging baseline and wheel version numbers connected; on the compiler side, advanced FlagTune managed Manifest and runtime compatibility handling, established an iluvatar3.6 baseline and test workflow for Iluvatar, unified the backend initialization interface for the FlagGems test template, and exposed synchronization scope and memory order as explicit parameters in the tle.signal and tle.signal_wait frontends (corresponding to the FEP-0096 distributed primitives direction); additionally, CommonIR conversion integrated Triton 3.6, tle_raw optimized the sort operator, Hopper WGMMA cross-dtype accumulator reuse, and XPU-side do_bench divide-by-zero fix.
  • FlagCX: On the delivery side, packaged libflagcx.so into the wheel, unified the Iluvatar build key, switched Nexus upload to a shared workflow, and added Fedora 43 to the Nvidia RPM matrix; on the interface side, widened the lane mask from 32-bit to 64-bit (reserving headroom for chip-scale expansion); on the tooling side, changed PTD performance log conversion to streaming (avoiding memory exhaustion under large-scale stress testing) and corrected the KV-equivalent throughput metric; on the backend side, integrated the DAMO XuanTie PPU (in two steps: CI and torch plugin) and added the default path for the Iluvatar device API.

Inference and Training Frameworks

  • Torch-FL: After six-platform FlagGems-first rollout, the week was spent on follow-up workarounds, switches, and gating—named workarounds (MetaX slice operators, MUSA complex rotary position encoding kept on the device side), explicit switches (CI pinned back to the last usable FlagGems commit, USE_FLAGTUNE=0, build-time accelerator configuration written into the wheel), and gate construction (PPU detection, platform manifest externalized, all platforms tracking FlagGems master); environment variables were unified under a single FLAGOS prefix; the decoupled DCU wheel fixed torch.cuda availability; the final stretch of the window focused on Qwen-Image 2.1 and 2512 performance across multiple chips (GCU single step reduced to 7.1 s/it, DCU scheduling overhead continuously reduced, ultimately producing throughput curves and tail latency measurements).
  • FlagGems-vllm: Hygon and DAMO XuanTie comparative implementation of moe_sum; Moore Threads MTT S5000 added persistent_topk; Ascend added SparseAttnSharedKV (DeepSeek-V4 sparse attention structure, a single commit of +9637, six fixed shapes, with accuracy as the acceptance criterion) and persistent_topk, and consolidated vendor operators into a unified directory; fused Marlin MoE (INT8 / FP8 two W8A16 weight variants) and FP8 variable-length FlashAttention-2 filled in the two real-world forms on the inference side: “variable-length batching and MoE sparse activation”; the final stretch of the window continued with MUSA’s fused_q_kv_rmsnorm, MetaX varlen attention, and Ascend kda_gate_cumsum.
  • FlagGems-sglang: Served as the landing channel for competition results—on 09-14, 10 competition branch PRs were merged into the main repo in a single day (bmm-chunk, decode-attention, fused-rmsnorm-warp2, task19 / task21-moe-sum-reduce, etc.); subsequently built in upstream test tooling, imported multimodal rotary position encoding fused operators, changed do_bench to a single function dispatched by vendor, registered the moe_fused_mul_sum competition operator and provided a batch of batch3 reference, tests, benchmarks, and documentation.
  • vllm-plugin-FL and sglang-plugin-FL: The former enabled the Hygon vLLM 0.24.0 workflow, integrated metax CI, raised Enflame S60 and Kunlunxin to the 0.24 line, integrated DAMO XuanTie PPU CI, fixed Kunlunxin FlashAttention state pollution, and adapted Iluvatar BI-V150; the latter built CI pipelines for Hygon DCU and Enflame GCU respectively (the Hygon line builds FlagCX v0.13.0 with the AMD adaptor), decoupled dispatch unit tests from platform configuration, and added benchmarks for preloading.
  • FlagScale and training kernel line: FlagScale unified the mutually coupled CI dependencies across accelerator platforms and fixed fork PR dependency artifact cache isolation; TransformerEngine-FL cherry-picked fixes from mainline; Megatron-LM-FL replaced hardcoded CUDA device operations with platform-aware APIs (covering optimizer, initialization, training, and tooling paths); FlagScale-Agent hardened the agent harness; FlagPrism unified operator acceptance tests and added Enflame debugger and TOPSPTI performance analysis support.

Release Engineering and Governance (build-infra / community / docs)

  • build-infra: In addition to the version bumps and image line in Section II, this week also added the FlagCX wheel packaging line (build, verify, publish in three steps), recorded the Hygon rc2.post1 dual-image tags and re-verified them, documented the Hygon gflags header dependency pitfall, and made paired recording of image tags and version labels the direct evidence for each backend entering the 2.2 delivery scope.
  • community: 2.2 release governance moved from a manual dashboard to automation (syncing issues to the org project view every 15 minutes, deriving release status from linked PRs, and writing RC verification rules into the documentation); maintenance of 20 FEPs and the RC2 checklist was driven by the release manager line.
  • docs: The documentation line was folded into this round of CICD transformation (new/flagcicd branch merged with main), and the online lab help content was updated in two rounds.

Quantum and Emerging Directions

  • FlagQuantum (one of the fastest-accelerating directions this week): On 09-14, completed Twin API freeze and QPU digital twin historical sequence management (calibration and verification history, candidate comparison, sequence restoration into chains) within a single day; subsequently graded Twin evidence by circuit topology, integrated JAX frontend tests and wrote coverage floors into the contract file (raised in two tiers from 60% to 75%), enforced package-level strict type checking, and landed the quantum error correction record layer (decoupled from specific encoding schemes); in the final stretch of the window, a single contributor continuously laid down algorithm primitive packages, from quantum Fourier transform, phase estimation, Grover search, and amplitude estimation all the way to QUBO-to-Ising mapping, quantum kernel methods, quantum PCA, k-medians, and other application-layer primitives.
  • FlagTrain: New repository established on 09-16 (placeholder repo, 5 KB in size); another slice carved out on the training side, with code landing yet to be observed.
  • Open3D-PIMC: Open-sourced on 09-14, code landed on 09-16 (662 entries: the pass system and compilation cache keys of the compilation layer raisa-inductor, the C++ runtime rcs2; the README spells out four gaps to be filled: memory hierarchy, sharding topology, dynamic inference, and compilation artifact reuse); directly related to the FlagOS 3D compute chip direction, not in the 2.2 acceptance scope.
  • flir (FlagTree IR): Aligned with upstream bufferization semantics (removed the Pure marker from tile.to_tensor), fixed memory effect markers, and unified the triton version identifier convention.

IV. Member Units and Vendor Adaptation

  • Hygon: Four workstreams in parallel — quantization (W8A8 INT8 GEMM), TLE enablement, fused rrelu backend kernel, and DCU FlashAttention forward/backward fixes; decoupled the DCU wheel to fix torch.cuda and the Qwen-Image stream; FlagSparse DCU line (sddmm testing, spgemm precision separation); enabled the workflow for vLLM 0.24.0; completed rc2.post1 re-verification and post2 rebuild on the dtk26.04 image.
  • Ascend: The densest operator line for MoE and linear attention — SparseAttnSharedKV, persistent_topk, kda_gate_cumsum, grouped_topk (via the TLE DSA raw interface), dedicated linear operators, swiglu, and grouped_matmul; the CommonIR proof of concept is marked as implemented in FEP (limited to the Triton 3.5 line on 910B / 910C); the FlagTree wheel upload path is now working; four image variants (cann8.5.0 / cann9.0.0) rebuilt with cann-shmem added.
  • Moore Threads: Two quantization paths landed — native FP8 W8A8 matmul and W8A16 FP8 RMSNorm; persistent_topk on MTT S5000 and device-side execution of MUSA rotary position embedding; FlagTree jumped to 0.7.0rc2+mthreads3.6; the first plugin-enabled 0.20.2 image is complete; FlagPrism’s profiler and debugger integrated into the compiler chain.
  • MetaX: W8A16 RMSNorm, FP8 topk routing, varlen attention optimization, and masked_fill out-of-bounds fix; enabled metax CI for vLLM and bumped to the 0.24 line; FlagSparse MACA line adaptation; on the industry side, completed Day0 adaptation for Shanghai AI Laboratory’s ATRIA Dawn Preview (37 flagship models cumulative by company count), with the interim report turning profitable, the 09-17 lock-up expiry window, and stock price movements recorded as capital-market items.
  • Enflame: Vendor branches synced back to mainline in batches; S60 adapted to the vLLM 0.24 line, GCU CI pipeline, GCU300 recorded in the 0.24.0 report; FlagPrism added the Enflame debugger and TOPSPTI support; two tops images rebuilt; financing and IPO commentary continues (09-11 listing on the STAR Market).
  • Iluvatar CoreX: Unified iluvatar build key, merged the device control interface /dev/itrctl, FlagTree established the iluvatar3.6 baseline and test workflow for it; FlagDNN platform architecture reorganized and test surface converged; adapted to the vLLM 0.24 line; corex4.5.0 image rebuilt.
  • Kunlunxin: A batch of roughly ten backend fixes in a single day (grouped_mm persistent kernel, SDPA, mse_loss, etc.) cleared out recent operator regressions; xCCL packed into the base image; sum migrated to tle.gpu; fixed state pollution in FlashAttention module imports; proactively reverted the tle.raw fast path and the 0.6.1+xpu3.6 pin that had not yielded stable gains; xpu tag iterated to 0.7.0rc3+xpu3.6.
  • DAMO XuanTie: PPU backend enabled TLE in FlagGems, integrated CI in FlagCX and vllm-plugin-FL (including the torch plugin), and explicitly probed in the Torch-FL gate; added moe_sum variants and received KernelGen operator handoff; already reserved a slot in the FlagTree 2.2 multi-backend plan (FEP-0098), with deepening dual-line participation.
  • Tsingmicro: Open3D-PIMC open-source release and code landing (co-developed with BAAI); distributed primitives enabled in the backend, converging with the 2.2 TLE distributed roadmap.
  • Horizon Robotics: Its subsidiary D-Robotics completed a $400 million Series C round, the heaviest industry event for the member ecosystem this week.
  • BAAI (lead party): Led RC2 governance and FEP governance implementation, defined release boundaries for 20 FEPs, co-developed Open3D-PIMC, and articulated the “define hardware form factor” direction; both release artifacts and governance cadence advance around its leadership.

V. Ecosystem and Community

Competitions and Open Contests

  • SGLang cross-chip operator optimization contest output continues to land in the main repo: 10 contest branch PRs merged into FlagGems-sglang on 09-14 alone; in the latter part of the window, contest operators such as moe_fused_mul_sum were registered and ingested (#87), with batch3 references, tests, benchmarks, and documentation all landed. The contest is becoming FlagOS’s常态化 external operator supply line.
  • FlagOS and MiniCPM Model Inference Throughput Optimization Challenge: development and submission phase from September 21 to November 20, 2026, with review in early December; targeting inference throughput optimization on the FlagOS stack, it continues the community contest system after the operator optimization contest.

Conferences and Open-Source Releases

  • 2026 AI Open Computing Conference and Zhongzhi FlagOS Technology Conference: held October 17–18 at the Zhongguancun National Independent Innovation Demonstration Zone Exhibition Center in Beijing, themed “One Stack Through, Boundless Intelligent Computing,” with registration opening 09-18; workshop topics (KernelGen, edge, TLE Attention, FlagScale-Agent) map one-to-one to this week’s engineering observations.
  • Open3D-PIMC open-source release: announced at the China Computing Conference on 09-14, code live on 09-16; co-developed by Tsingmicro and BAAI, positioned as one of FlagOS’s primary solutions for next-generation 3D computing chips, with optimization results previewed for release at a top global tech conference in Q4.

News and External Channels

  • Component-level news search: eleventh through fifteenth consecutive quiet windows: zero valid hits across 24-hour windows throughout the week; external factual developments are based on the GitHub org and community channels (BAAI Community, Zhihu institutional account, CSDN column); member-unit coverage visible externally centers on capital markets and Day0 adaptation of their own stacks.
  • Inclusion boundary note: third-party content on the BAAI Community platform with no interface to this stack (such as the Zidong Taichu model open-source post) is not counted; pure market commentary and stock price movements are recorded as background only.

VI. Trend Observations

  • 2.2 enters the release artifact freeze and assembly phase: three things completed in sync — the global switch (version 2.2.0) landed, all-backend images rebuilt in batch, and release artifacts made verifiable; only one week remains in the test period, with residual risk concentrated on “installs and runs correctly” rather than feature gaps, and the Go/No-Go basis shifting from “humans reading checklists” to “derivable state.”
  • The dispatch layer becomes the fulfillment layer for “one operator library reused across chips”: the six-platform FlagGems-first approach yielded its first complete quantification (the PPU line settled at 435 FlagGems routes versus 1,601 vendor kernel routes), and the length of the bypass list (47 PPU items, MetaX slicing, MUSA complex rotary position embedding, missing FlagTune on the CUDA side) is an inverse indicator of cross-chip reuse rate; “routing plus bypass list, plus gating” becomes a reusable mechanism template.
  • Multi-backend adaptation forms diverge: moving up and swinging back coexist: Moore Threads getting a FlagTree jump and its first plugin-enabled image, and Ascend’s wheel upload path working, count as moving up; NVIDIA / MetaX / Enflame pinning back to 0.6.x and Kunlunxin reverting the tle.raw fast path count as swinging back — the latter shares the same origin as the RC discipline of “rather not fix than break a verified cell,” a signal that platform adaptation has entered a stable phase.
  • Operator expansion has two clear mainlines, with the bottleneck shifting from writing kernels to registration and acceptance: quantization (W8A8 / W8A16 / FP8, expanding from matmul to normalization and sampling) and MoE / linear attention (grouped matmul, swiglu, sparse shared KV, gated Delta rule) map directly to the real structure of current inference models; the export checks, test tagging, benchmark alignment, and acceptance framework restructuring that accompany KernelGen’s batch ingestion show the expansion bottleneck has shifted to registration and acceptance.
  • Test and quality infrastructure is becoming platformized: DAMO XuanTie’s PPU onboarding to multiple CIs, Iluvatar CoreX establishing the iluvatar3.6 baseline, FlagTree extracting a unified backend initialization interface, and FlagQuantum tightening coverage floors and type checks — different forms of action point to the same goal: having every backend continuously verified in CI rather than relying on manual passes.
  • The outline of the next version is taking shape in the documents, and ecosystem operation density is about to rise: RISC-V experimental support, edge SDK, OS packaging, and embodied intelligence and AI for science working groups have appeared in FEP planning, with new backends from T-Head, Enflame, and Moore Threads entering the FlagTree 2.2 plan; the FlagTrain repo creation, FlagAudio moving to implementation, and Open3D-PIMC landing show new directions continuing to branch out; the October conference and the challenge contest opening in late September will significantly raise ecosystem operation density, with the next reporting peak expected at the 09-28 release window.

Appendix: Sources and Verification