Reporting period: Monday, October 26, 2026 to Friday, October 30, 2026, 5 working days in total.

Sources: 5 issues of this publication’s daily FlagOS update reports (10-26 / 10-27 / 10-28 / 10-29 / 10-30, with no missing issues during the period). The 10-26 issue is the Monday morning report, whose research window starts from the previous issue’s cutoff at 10-23 06:00, spanning 72 hours and covering the weekend of 10-24 and 10-25; the four issues from 10-27 to 10-30 use 24-hour windows that are contiguous, with the final window running from 10-29 06:00 to 10-30 06:00. Therefore, the factual interval of this report is 10-23 to 10-29, with the 10-23 to 10-25 portion labeled by its original dates.

Editorial note: Organized along five dimensions: versions and releases, component and code co-building, member units and vendor adaptation, ecosystem and community, and trend observations. Summed across their respective windows, the five daily reports total 1,187 commits and 755 merges; counting only the four complete 24-hour windows (10-27 to 10-30), the totals are 575 commits and 481 merges. The number of repositories with pushes in each issue was 16, 18, 20, 23, and 21 respectively, out of 61 organization repositories in total. Versions and tags were independently re-verified against the tags and Release atom sources of each component repository; the 10-31 verification result: the latest tag of build-infra remains v2.2.0, and the release/2.3 directory in the community repo still contains only the Chinese and English schedule tables, with no release manifest found.

I. Weekly Highlights

  • 2.3.0 completes the entire pipeline from runtime to application layer, but tags and release manifest still not in place (10-25 ~ 10-30): On 10-25, the 2.3.0 runtime was authorized for rebuild by version; on 10-26, twenty vllm0.24.0 application images were authorized for rebuild on the new runtime, and tags were consolidated from “backend-specific suffixes” into a unified 2.3.0-0.3.0; from 06:54 to 13:25 on 10-27, twenty consecutive bot commits recorded the application image tags for the twenty backend keys one by one; from 10-28 to 10-29, the changelog went live on the site page and Harbor. As of the morning of 10-30, the latest build-infra tag is still v2.2.0 from August 3, and community/release/2.3 still has no release manifest. Per schedule, 11-13 is the FEP merge deadline, 11-30 is feature freeze with rc0 pulled, 12-07 rc1, 12-14 rc2, 12-25 final seal, 12-30 release.

  • MiniMax-M3.1-Flash nine-chip W8A8 delivered same day, Day-0 enters the “unified-format batch replication” phase (10-23): On the day of MiniMax’s open-source release, FlagOS published W8A8 versions for nine chips on ModelScope and Hugging Face, with all nine repos created within half an hour between 14:06 and 14:39 on 10-23. The nine are DAMO XuanTie (Zhenwu), NVIDIA, MetaX, Hygon, Huawei Ascend, Moore Threads, T-Head, Kunlunxin, and Tsingmicro, with NVIDIA, Ascend, Kunlunxin, and DAMO XuanTie offering Express versions. The technical approach was to convert the model’s original QAT NVFP4 weights into a cross-chip unified W8A8 format; the source deployment example uses DAMO XuanTie as the baseline (vLLM 0.24.0, vllm-plugin-FL 0.3.0, FlagGems 5.4.0, tensor parallelism with 8 cards). This is the second “nine chips simultaneously on model open-source day” within a week, following GLM-5.3-Flash nine-chip; the difference is that the previous round ran BF16 and multiple precisions in parallel, while this round converges to a single W8A8 path.

  • Horizon BPU becomes a per-operator-executable PrivateUse1 backend for the first time, new platform goes from “unusable by design” to usable (10-28): Torch-FL #674 landed the per-operator execution layer (31 files, +5698 / -145). Previously, BPU registered no compute operators on PrivateUse1; hbDNNInferV2 only accepted a fully compiled graph, every aten call fell through to cpu_fallback, and backends_bpu.conf was empty. This PR fills in the missing intermediate layer: on the x86 side, hbdk4 compiles a per-operator .hbm artifact library, generates C++ kernels that commit these artifacts, and adds a drobotics conf route, covering 40 elementwise operators (32 unary, 8 binary) and 11 shape buckets, with all 440 artifacts on RDK S600 compared one by one against NumPy with zero differences. Three follow-up commits fixed the distribution log name, the CUDA copy kernel guard, and the vendor-name-to-platform-id mapping. The limitation is equally clear: backbone operators such as convolution still rely on the torch.compile full-graph path.

  • FEP-0140 changed to single release on 0.32, 0.28 skipped, AMD added, rules surface eliminates version-chasing cost in one pass (10-27 ~ 10-28): Two rewrites in the community repo (#157, #158) set the vLLM plugin’s multi-version compatibility strategy to “0.32 becomes the sole release version and covers all chips,” expanding the original scope of “five vendors selected by Day-0 demand” to the full matrix (the ten vendors of the 2.2 cycle plus NVIDIA and AMD); 0.28 is no longer a release version, with the matrix column and related PR sections deleted entirely, and already-merged 0.28 adaptations retained only as an upgrade baseline. On 10-28, profiling scope and validation plan were added (#159), and the status was changed to Implementable with Owner set to @ceci3 (#160); FEP-0141 was narrowed to SGLang 0.5.18 and basic functionality for MetaX and Tsingmicro (#161). The cost is stated explicitly: adaptations merged on 0.28 need to go through acceptance again on 0.32, and this workload is not yet reflected in any PR.

  • DAMO XuanTie fills two foundational gaps within a week: BLAS1 fifteen operator groups landed and PPU sparse attention (10-26 / 10-28): On 10-26, FlagBLAS #154 added fifteen Level-1 basic linear algebra operator groups in one pass — AMAX, AMIN, ASUM, AXPY, COPY, DOT, DOTC, DOTU, NRM2, ROT, ROTG, ROTM, ROTMG, SCAL, SWAP — touching 17 files with 16,168 new lines; previously this backend’s presence in FlagOS was concentrated in the inference path, with the numerical library a blank. On 10-28, FlagAttention #111 added MiniMax sparse attention inference operators for Zhenwu PPU (6 files, +4644 lines), supporting paged KV cache, causal masking, and forced block selection, with prefill passing 21/21 at a geometric mean of 2.299x and decode passing 18/18 at a geometric mean of 1.354x, for a total of 39/39 at a geometric mean of 1.800x. Measured against the three stages of “can run inference, can run training, numerical library self-consistent,” this week crossed the first step of the third stage.

  • MetaX moves acceptance evidence for 135 specialized operators into reviewable state, opening 135 PRs within an hour (10-27): FlagGems-Experimental opened #744 through #878 between 17:43 and 17:59, all titled “Add MetaX support for ," each a single file with roughly 200 lines changed. The PR description states this round is a retest of MetaX specialized operators (1027 batch): 150 operators participated, 135 passed three rounds of retesting and were submitted one by one, and the 15 that failed were left out of the batch; acceptance criteria were all 29 precision cases passing and a performance geometric mean of 1.008x (threshold 0.8), on an environment of torch 2.8.0 plus metax3.7.2.0, flagtree 0.6.1, and eight C550 cards. That day the organization's open PRs rose from 225 to 401, of which 135 came from this single batch submission.

  • Test infrastructure ref-as-candidate lands in two repos, “what to test” shifts from whether an operator exists to whether reference and implementation agree (10-29): FlagGems #7630 (9 files) lets correctness tests and benchmarks run an explicitly declared reference implementation as the candidate, no longer relying on external candidate files; missing references, non-callable references, and test bodies that do not actually invoke the candidate all fail explicitly. On the same day, FlagGems-sglang converted all correctness suites to get_candidate across eleven PRs #239 to #249, and added a daily automatic sync PR from master to kernelgen-dev (#242, two already generated that day); another 57 test fixes by the same author merged that day, covering skip conditions and reference ABIs for Ascend, MetaX, Enflame, Kunlunxin, and NVIDIA. This line produces no operator counts, but determines whether all subsequent backend alignment is trustworthy.

  • MiniCPM-OCR dual models achieve Day0 coverage on 12 platforms, first comparable normalized metrics (10-29): MiniCPM-OCR 1.0 (1.3B) and MiniCPM-OCR Jev (2B), open-sourced by ModelBest and OpenBMB, completed cross-chip adaptation, covering 12 platforms: DAMO XuanTie, NVIDIA, Huawei Ascend, Hygon, Kunlunxin, MetaX, Moore Threads, Tsingmicro, T-Head, Xiwang, Mac (ARM), and This Chip Technology. Performance metrics are stated separately: Jev averages 63.56 ms on DAMO XuanTie, with actual compute throughput reaching 98.7% of native NVIDIA H100; OCR 1.0, normalized by peak compute, achieves single-document P50 throughput at 169.3% of native and 137.1% in batch scenarios, with the explicit caveat that the 169.3% premise is higher utilization on low-peak-compute platforms rather than a faster single card; on the edge-side M5 CPU, Jev averages 1.2 seconds per page-block discrimination with a median of 895 ms.

II. Versions and Release Activity

This Week’s Tags and Release List (Beijing Time)

Time Component Tag / Version Notes
10-26 10:13 FlagTree 0.7.1a1+mthreads3.6 Moore Threads 3.6 dedicated build line, tag only, no corresponding Release body
10-28 17:25 FlagCX v0.14.1 Points to #668 “generate device bitcode per adapter”, git tag only, no Release body
10-29 10:55 FlagCX v0.14.1 (tag retargeted) On review the tag had moved to the merge commit for #683 (Kunlunxin cstddef backport), still no body
10-29 11:09 FlagTree 0.7.1a1+tsingmicro3.6 Tsingmicro 3.6 dedicated build line, tag only, no corresponding body
  • Three tags, two components, none a formal release: no component shipped a formal version this cycle. FlagGems remains on 5.4.0 (09-28) as the formal line, with 5.5.0.dev0 opened on 10-12 but no new tags since; FlagQuantum uses v0.3.1 (10-16) as the quantum stack baseline; FlagScale, FlagBLAS, FlagDNN, FlagFFT, FlagTensor, FlagAttention, vllm-plugin-FL, sglang-plugin-FL and others remain on the 09-28 batch. This is the typical gap between the 2.2 release and 2.3 GA on 12-30: public versions are silent while artifact and build lines stay active.
  • Two tags missing release bodies is the week’s only recurring process issue: FlagCX v0.14.1 created only a git tag without a GitHub Release, inconsistent with v0.14.0’s practice of pointing its body to the FlagOS 2.2 release list; FlagTree’s 3.6 line advances as “one tag per vendor”, and 0.7.1a1 itself has no unified release notes, so downstream can only infer the backend and Triton version from the tag name.

2.3.0: Pipeline Runs End to End, Only Tags and Release List Missing

  • Runtime layer (10-25 ~ 10-26): On 10-25 the 2.3.0 runtime was authorized for rebuild on version request, followed by two fixes for quoting in the OCI tag build arguments and for vendor SDK environment variables losing the venv prefix; the container gained startup-time version parameters, allowing FLAGTREE_VERSION=latest to install that day’s build and FLAGGEMS_VERSION to pin the FlagGems version, turning versions from “baked into the image” to “selected at startup”, and the -build variant was removed.
  • Application layer (10-26 ~ 10-27): On 10-26 #1488 added pending-release changelog entries for the twenty vllm0.24.0 application images to satisfy the gate, while moving native plugin tags out of image tags and into a unified resolver, making the unified tag 2.3.0-0.3.0 without a backend suffix valid. On 10-27 twenty bot commits recorded the tags for twenty backend keys one by one: Ascend cann8.5.0, cann8.5.0-910c, cann9.0.0, cann9.0.0-910c; Cambricon neuware4.4.3, neuware4.7.2; Enflame tops1.9.10, tops1.10.6; Moore Threads musa4.3.6, musa5.2.0; MetaX maca3.7.2.1, maca3.8.1.3; Iluvatar corex4.4.0, corex4.5.0; NVIDIA cuda12.8, cuda13.3; plus Kunlunxin xre5.37.1, Hygon dtk26.04, Tsingmicro tsm260610, and Sunrise tangrt1.2.0.
  • Traceability and gates (10-28 ~ 10-29): Each image’s changelog now appears both at the end of the site page and in the Harbor repository description (#1545, 455 files, +19080 lines), with the reason field made bilingual in Chinese and English (#1542); the application page consistency check was wired into pre-commit and CI (#1549), so changing an image_tag or changelog reason requires rebuilding images.yaml before comparison.
  • Outstanding items: version tags not cut, release list not created. The 10-30 daily report recorded the state as “release/2.3/release-2.3.yaml in the community repo is still 404”, and the 10-31 review found the directory still contains only the Chinese and English schedule tables, code of conduct, governance and maintainer docs, with no release list.

AMD ROCm 7.2.4: The Cycle’s Only New Backend

  • Base image (10-26): ROCm 7.2.4 installed directly from repo.radeon.com on ubuntu 24.04, with only 28 lean packages, totaling 94 after apt resolves runtime dependencies, explicitly excluding MIOpen, MIGraphX, rocm-gdb, rocprofiler-sdk and opencl; rehearsed in a clean container and validated with eight W7900 passthroughs on a local image. The rehearsal surfaced two facts that had to go into the Containerfile: nodes cannot reach archive.ubuntu.com, so a domestic HTTP mirror must be switched in before ca-certificates exists (HTTPS fails the handshake); and the pin file is a requirement, not a version preference.
  • Configuration and packaging (10-27): Added vendors.amd.rocm7.2.4, with a stack of torch 2.11.0+rocm7.2, triton-rocm 3.6.0, flagtree 0.7.0+amd3.6, hardware labeled Radeon PRO W7900 (gfx1100, RDNA3), driver 6.16.13, Python 3.12; five consecutive commits added hipsolver, hipfft and miopen-hip dev packages, enabled the FlagCX AMD wheel line and vendor PyPI, and validated on sixteen local gfx1100 cards. The native deb and native rpm lines gained an arm64 dimension in the same period.
  • Runtime connectivity (10-29): FlagCX #679 got SGLang tensor parallelism working on ROCm — adding an eventElapsedTime implementation, mapping torch.bool to flagcxUint8, and adding a USE_AMD test build branch; on dual R9700 cards AllReduce, ReduceScatter, AllGather, Broadcast, Send/Recv and graph-captured AllReduce produced correct results, and Qwen3.5-9B and Qwen3.6-35B-A3B-FP8 can serve at TP=2.
  • Builder catch-up (10-29): The FlagCX wheel built on the 7.2.4 runtime linked against GLIBC_2.38 and was rejected by the wheel line’s 22.04 gate, so that line got a self-contained 22.04 builder (jammy suites plus deadsnakes Python 3.12 and a pinned torch), bringing the glibc floor back to 2.35.
  • Boundary: FlagGems still has no ROCm/HIP C++ backend, so AMD goes only through the Triton path for now. This is direct evidence that the backend matrix is still expanding rather than converging this cycle.

FlagCX: From Tags to Distribution Packages

  • Device bitcode generated per adapter (#668, merged 10-18, the content of v0.14.1 this week): The hardcoded bindings/ir/nvidia in the setup.py bitcode step was replaced with a per-adapter lookup, each adapter declaring its own Makefile and architecture variables. Previously any non-NVIDIA adapter would throw a RuntimeError or silently produce no bitcode, and FlagTree’s iluvatar backend could only copy FlagCX sources and rebuild on its own.
  • rpm line expanded from three backends to six (#673, 10 files, +295/-8): Added libflagcx-tsm (Tsingmicro), libflagcx-sunrise (Sunrise) and libflagcx-du (Hygon DCU). None of the three needs a vendor base image — the SDK is unpacked to /opt or /usr/local without invoking a package manager, and an openEuler image plus a file repo is a complete build environment; vendor sonames are filtered uniformly per the existing Ascend convention.
  • Delivery surface shifts to the wheel line (10-29): The build-infra bot recorded the flagcx wheel release (#1553), humans filled in five empty descriptions and added flagcx==0.14.1+rocm7.2.4 (#1556), then pinned hygon-dtk26.10 to flagcx==0.14.1+dtk2610 (#1563). The 0.14.1 delivery surface now covers cuda12.8, cuda13.3, corex4.4.0, corex4.5.0, xre5.37.1, rocm7.2.4 and the new dtk2610.
  • The 0.14 series is still within its support window: The in-review #683 backports the Kunlunxin cstddef fix to the 0.14.0-rc2 line, showing the 0.14 patch line is not frozen.

FlagTree: The 3.6 Line Sliced by Vendor

  • Two vendor-specific tags: 0.7.1a1+mthreads3.6 on 10-26 and 0.7.1a1+tsingmicro3.6 on 10-29 belong to the same “vendor-sliced 3.6 pre-release line”, both without Release bodies. The Tsingmicro tag corresponds one-to-one with #1459 merged the same day (Tsingmicro backend synced to the internal Triton 3.6 development line, 27 files, +2264/-407).
  • Capability gains concentrate in the compiler: Moore Threads’ [MThreads][TLE] persistent GEMM pipeline and SPMC synchronization landed on mainline (#1294, 63 files, +6192/-403), merging the two compiler sets previously serving addmm/baddbmm and bmm into one superset, supporting stage and phase advancement in dynamic loops, one producer to many consumers, named and implicit reads, segmented completion and consumer epoch derivation, plus single-issue, fused-consumer and 16-warp persistent paths; Ascend gained the TensorView access path (#1426, 32 files, +4901 lines); AMD optimized batch-1 decoding for Qwen3-1.7B bf16 (#1439, 44 files), with R9700 at 154 tok/s at context 1 and 125 at 8K, and W7900 at 167 and 136 respectively, measured bandwidth 530 to 597 GB/s, 82% to 87% of that card’s measured streaming ceiling.
  • IR-layer work: flir added a TensorView dialect (#83, 25 files, +1396/-13), turning Triton pointers into tensor_view carrying shape, stride and access encoding, providing partition, strided and gather/scatter encodings, wired into CommonIR’s tile.load and tile.store, sitting between the Triton tt dialect and HIVM/Ascend NPU IR, parallel to TileIR.
  • Under review: SpacemiT’s vmt4d backend (#1455), Kunlunxin’s distributed TLE backend (#1436), Hygon TLE communication primitive adaptation (#1441), the Ascend rpm line switched to consuming published wheels (#1461, the first line needing neither vendor SDK nor hardware), and four NVIDIA Hopper software pipelining defect fixes (#1460).

III. Components and Collaborative Code Contributions

Organizational Cadence: Five Periods Accumulate 1,187 Commits and 755 Merges

Period Window (Beijing Time) Repos Pushed Commits Merges In Review (Updated Within Window) Newly Opened
10-26 10-23 06:00 ~ 10-26 06:00 (72 hours) 16 612 274 253 141
10-27 10-26 06:00 ~ 10-27 06:00 18 185 133 225 74
10-28 10-27 06:00 ~ 10-28 06:00 20 102 98 401 269
10-29 10-28 06:00 ~ 10-29 06:00 23 99 67 288 101
10-30 10-29 06:00 ~ 10-30 06:00 21 189 183 253 84
Total — — 1187 755 — 669
  • Merges by repo (cumulative, per daily report disclosure): FlagQuantum 226 (29.9%), FlagGems 224 (29.7%), build-infra 75 (9.9%), FlagGems-sglang 59 (7.8%), Torch-FL 33 (4.4%), FlagGems-vllm 29 (3.8%), FlagTree 24 (3.2%), vllm-plugin-FL 16 (2.1%), optest 12, FlagTrain 10, FlagCX 10, FlagAttention 9, sglang-plugin-FL 5, community 5, FlagQAI 4, and 2 each for FlagBLAS, FlagScale, FlagOps, and TransformerEngine-FL, plus 1 each for FlagCV, FlagSparse, FlagPrism, flir, Trident, and FlagTensor.
  • Dual-engine share falls below 70%: FlagQuantum and FlagGems together account for 450 merges, or 59.6%; adding build-infra brings the top three repos to 69.5%. In the previous period, the same two repos accounted for 56.3% and the top four for 79%. This cycle, build-infra’s share rose to nearly 10% due to the 2.3 image accounting.
  • Weekly pattern: “two peaks, one trough, one rebound”: Monday (72-hour window) saw both the quantum stack and FlagGems at highs; Tuesday the quantum stack continued climbing while FlagGems absorbed the load; Wednesday shifted mainly to build-infra accounting (36 merges, 20 of which were image-tag bot commits); Thursday fell to 67 merges, the week’s low; Friday rebounded to 183 merges, the week’s high (FlagGems alone contributed 92).
  • The two in-review spikes both relate to batch submissions: Of the 401 in-review items on 10-28, 135 came from a MetaX operator batch PR and 269 were newly opened. After falling to 288 on 10-29, the count dropped further to 253 on 10-30. Excluding batch submissions, the actual review queue fluctuates between 220 and 290 items, with a higher median than the previous period (154 to 239).

FlagGems (224 Merges): Automated Supply and Correctness Fixes in Parallel

  • Operator supply is now handled by KernelGen: On 10-26, 16 KernelGen operators with the NVIDIA prefix were merged (one category each for sparse and structured, quantization, special functions, and tensor metadata). On 10-29 alone, 22 auto-generated operators landed (unsafe construction and reset of sparse tensors, nnpack spatial convolution, thnn convolution, fractional max pooling backward, cholesky, frobenius norm, chain_matmul, and a batch of edge-case operators), with five more opened the same day—the queue continues. Human effort goes not into writing operators but into launch parameters and test executability.
  • The correctness mainline is the week’s most valuable class of commits: The address arithmetic shared by index_put and _index_put_impl_ was changed to a wide type (#6892, two files, +112/−4 lines). Previously, on DAMO XuanTie PPU-ZW810E, int32 indices with large-stride tensors silently wrote to the wrong address—the target row was unchanged but guard prefixes within the same allocation were overwritten. The root cause: index-times-stride was evaluated in int32 and wrapped first, so converting only the final offset afterward came too late. On the Ascend side, flagtree was bumped from 0.7.0 to 0.7.1a1 with a new runtime validation script (#7837, five files, +291 lines), because the runtime image bakes flagtree into /opt/flagtree outside the virtual environment, so the pip-installed pin cannot override it. The Kunlunxin backend’s failure to import directly on current master was also fixed (#7803, 90 lines).
  • Backend tuning is densest on Kunlunxin: Eight out-of-place scalar-chain operators were converted to fused kernels (#7617, 275 lines)—single launch for small shapes, all pointers passed as kernel arguments, output allocated once and obtained via unbind; relative time improved from 0.083–0.126 to 0.813–0.934, roughly 7–10×. Batch-norm inference and QKV transform were converted to contiguous-segment kernels (#7600), with aggregate metrics improving from 0.228 to 1.357 and from 0.260 to 5.062, respectively. The integer-view fast path of masked_fill was rewritten in f32 form, improving from 0.577 to 0.829 on P800 (#7850, 594 test cases passing).
  • Other backends: Enflame’s conv_transpose2d was switched to seven hardware-tuned tiers indexed by data type, kernel size, stride, and output channels (#7036, +1886 lines), switching between direct-sweep and phase-specialized variants based on whether the output fits in L2. conv3d removed per-call channel zero-padding (#7061), with bit-identical output. MetaX added INT8 and FP8 grouped_mm_w8a8 (#6950, 7 files, +1220 lines); the benchmark shapes come from real call replays captured from GLM-5.2 on PPU SGLang TP=8—28 scenarios, 26 unique geometries, 3.24 million calls, 257 experts.
  • In-review structure: The 53 newly opened on 10-28 were mostly Enflame reference-implementation fixes (#7890 through #7908, consecutive numbers, covering Kaiser and inplace ldexp, aminmax, special_round, LU, vander and slogdet, median and stacking, Adagrad, batch-norm ABI), plus a one-line AMD fix—the vendor descriptor set the device name to cuda without providing triton_extra_name, causing pow, tanh, exp, rsqrt, erf, gelu, and others to all route through __nv_* and be rejected by the AMD backend. In the 10-29 window, FlagGems had 181 items in review, 60% of the organization, indicating that the bottleneck for multi-backend acceptance lies in reference implementations and test criteria, not operator supply.

FlagQuantum (226 Merges): From Structural Reorganization to Scenario Rollout

  • The week began with directory surgery: From 10-23 to 10-26, three days saw 505 commits and 148 merges, with this single repo accounting for 82.5% of organizational commits and 54% of merges. The QEC package reorganization ran through nine consecutive commits (#735 to #749): first auditing package boundaries and compatibility baselines, then sequentially isolating code matrices and noise sweeps, splitting code families and ownership, separating storage declarations from execution assembly, extracting the detector error model, separating decoding algorithms from optional adapters, finalizing package layout and installation guidance, and finally merging into main as a whole—directory surgery aimed at “installability.”
  • External dependencies take shape: The Quafu SDK lifecycle switch was completed in six commits (#852 to #866), with the discovery flow, logical tasks, physical program submission, topology resolution, and twin lifecycle each migrating to the SDK in turn, finally retiring the old execution lifecycle. The old path was deleted rather than kept as an alias—a hard switch. In the same period, Rydberg presence went from establishing the contract (#854) to rejecting observations in unconditional assembly (#865), encoding single-shot presence observations (#869), validating bounded coherent branch references (#873), and finally proposing finite dynamic coherent references (#876).
  • Mid-period shift to physical scenarios: The ten merges on 10-27 included expectation-value contraction of Module Hamiltonians under tensor networks (#939), fixed-shots error-correction memory experiments (#932), and completion of fixed two-qubit gate coverage (#935). Among the six on 10-28, “whether sharded MPS is equivalent to unsharded” was turned into two-arm executable evidence (#945: max_bond 64 with exact gradients changes only layout; max_bond 2 with approximate gradients changes both layout and truncation; the difference between the two arms separates the two contributions).
  • The week closed on the synthesis pipeline: 10-29 saw 60 commits and 15 merges, all concentrated on quantum circuit synthesis (the CS series). Ten specification and delivery documents are archived in the repo as FQ-SYNTH-CS01..CS07-20261029: CS-01 defines semantic boundaries and validation for coherent integer construction, CS-02 lowers coherent addition with pure arithmetic kernels, CS-03 handles multiplication and coherent polynomials, CS-04 opens up restricted Python workflows, CS-05 adds lifecycle and workspace scheduling, CS-06 lands in three stages, and CS-07 moves into register semantics and program admission. The same day added portable .fqx experiment file save/load (#960) and checked program execution for fq.run (#964).
  • Assessment: The quantum stack’s working method is four-stage evidence—design draft, contract draft, runnable example, acceptance record. It is costly but highly verifiable, which explains why it has long accounted for over 30% of organizational commits but only about a 30% merge rate. It is unrelated to multi-chip adaptation and is the only software-stack mainline in the 2.x cycle decoupled from hardware.

build-infra (75 Merges): Image Matrix and Retractions

  • Image matrix accounting: On 10-27, twenty bot commits uniformly recorded the vllm application image tag for twenty backend keys as 2.3.0-0.3.0—the highest single-day merge count this cycle (36). Subsequently, per-image changelogs and push gates were added at the base layer, and three image-record loops were merged into one script.
  • Hygon DTK 26.10 eight-commit full chain (10-29): After the first container and config landed (#1554, #1555), the image was still neither buildable nor schedulable—base/hygon-dtk26.10 pointed /opt/dtk at dtk-26.04 while the SDK actually unpacked to /opt/dtk-26.10, and the build matrix lacked runner coverage for that entry, falling back to defaults (#1558). The global dependencies of torch 2.13.0+dtk2610 directly linked libmpi.so.40 and libibverbs.so.1, whereas the 26.04 wheel hashed these two sonames into the package, so the base image added libopenmpi3t64 (#1564) and the builder added libopenmpi3 (#1565). The same runtime pinned python 3.12, making the existing cp310 hcu wheel unresolvable, so the cp312 builder was rebuilt with deadsnakes 3.12 (#1562) and hcu-dtk2610 was added to the wheel release line (#1566). None of the eight commits touched the kernel—the cost of the hardware generation switch fell almost entirely on packaging and dependency resolution.
  • Two never-pushed images retracted (10-28): Harbor had no megatron_training0.18.2-cambricon-neuware4.7.2 or corresponding megatron_rl repo, yet the status matrix recorded image_tag: 2.2.0-0.3.0, and the docs pipeline published launch pages, readmes, and changelogs for two nonexistent images; thereafter every pubdoc-app returned 404 on these two repos. Root cause: in the 0.18.2 wheel, platform_register had no MLU platform; after torch_mlu’s gpu_migration aliased the CUDA surface to MLU, PlatformCUDA was selected, the pipeline parallel group was never initialized, and the MLU registration only landed on release/0.2. The remedy was to retract the claim rather than force a fit: remove image_tag, set launch_docs: false, and delete the two changelogs, restoring “changelog file set equals published set.”
  • Other: native deb and rpm gained an arm64 dimension (#1537); an Ascend rpm target (#1557, the first rpm line not dependent on vendor SDKs or hardware); vllm repackaging dependencies switched to reading the PEP 503 simple index (#1543, replacing one subprocess per dependency).

Torch-FL (33 Merges): Abstraction Layer Rename and New Platform Onboarding

  • Naming refactor in one pass: The boxing slot was changed from Backend::kCuda to Backend::kBoxing, each platform got a vendor name, source and CI directories, configs, flags, and packaging directories were renamed by vendor, backend enums and NVIDIA routing keys were renamed, and finally lookup mismatches left by the rename were fixed (six commits completed between 13:38 and 15:59). In the same period, “boxing must not be routed from default config” was made explicit, and a boxing-only day-0 config was added—turning “fall back to the packaging path when a platform lacks an operator” from implicit behavior into an explicit declaration.
  • Horizon BPU onboarding: See the first item in this week’s headlines; not repeated here.
  • Two hard fixes for “runs but runs wrong”: Hygon DCU’s runtime_dir previously pointed to a directory containing only ABI shims, so the runtime library was linked from 32 stubs—the build passed but import reported undefined symbols (#654, 71 files, 11k lines). Enflame’s bf16 GEMM fell back to host execution—a 2048×2048 bf16 mm measured 0.41 TFLOPS, below the same machine’s CPU at 0.54, while the same operator in fp16 was 80.2 and the vendor’s own torch was 84.6. Root cause: the support check did not include bf16, and mm and addmm copied transposed weights on the host side (#660); after the fix, it routes through the vendor BLAS.
  • Other: On the MPS side, preserve MPSGraph broadcast shapes, give linear operator test cases a CPU reference and readable diffs, and keep the Qwen3.5 vision factory and interpolation on MPS; Ascend follows FP32 matmul precision and keeps gradients resident (#683); route decoded soft-lowp combinations by conf key (#665); MUSA tuner threads through all strategy subclasses (#666); vendor name and platform id mismatches in build records (hygon/dcu, mthreads/musa, enflame/gcu, nvidia/cuda) were corrected together (#673).

Inference Stack: vllm-plugin-FL (16), sglang-plugin-FL (5), FlagGems-vllm (29), FlagGems-sglang (59)

  • Three new models entered the plugin within the same week: MiniMax-M3.1 support and inference examples (#631, merged 10-24), GLM-5.3-Flash pure public-operator implementation (#454, 90 files, +19140/−280 lines), and Qwen3.8-Flash-Next and Qwen4 checkpoint loading and model integration (#455, 65 files, +11226/−109 lines, including HC, PLE, QSA, and multimodal wiring). FP8 is uniformly capability-gated: if the platform natively supports it, native kernels are kept; otherwise it falls back to BF16 linear and MoE paths with --dtype bfloat16 forced.
  • Two upstream major-version lines advance in parallel: Native CUDA vLLM 0.32 adaptation (#615, 57 files, +3408/−1044 lines) pins the stack to vLLM 0.32.0 + cu129, PyTorch 2.13.0 + cu129, CUDA 12.9, and python 3.12.3; all six existing NVIDIA CI inference items and three serving items pass. Meanwhile, existing 0.28 adaptations continue to merge (Enflame S60 #582, Tsingmicro TXDA #642 in review), forming a parallel period with FEP-0140’s “ship 0.32, skip 0.28.”
  • Graph mode reaches the third and fourth domestic backends: Tsingmicro TXDA gained FULL_DECODE_ONLY graph capture and replay in the vLLM plugin (#649, eight files, +487 lines), fixing two root causes—kernel launches rejected within the capture domain (error code 0x47000003) and stream redirection caused by device guards—while non-TXDA paths remain byte-identical to upstream. On the AMD side, SGLang ran FlagOS on R9700 (gfx1201) (#157 in review).
  • The operator library’s focus shifts from additions to determinism: Fused all-reduce RMSNorm entered FlagGems-vllm (#773, 6 files, +3191 lines)—all-reduce plus residual add plus RMSNorm, optional FP8 static quantization, NVFP4 support on SM100+, and FP16 and BF16 at TP2/4/8. The ihc_pre stage1 merge replaced tl.atomic_add with per-split-slot writes (#1017), because atomic adds make results depend on block arrival order and are not bit-identical across repeated launches. On the MetaX side, FlashAttention cache safety and graph capture were fixed and TP2/TP4 optimized (#998), and MetaX TP2 packed decode got Split-KV scheduling and compute-tile reordering (#1025); fused_q_kv_rmsnorm landed on both Ascend (#872) and DAMO XuanTie (#888).
  • FlagGems-sglang is the cycle’s most merge-efficient repo: 34 competition-track operators merged in just over two hours (10-23 15:47 to 18:02, including nine within ten minutes from 16:21 to 16:31), supplied by multiple external contributors and covering MLA buffer read/write, layout reordering, Top-K sampling, MoE zero experts, cache positioning, and soft pooling. On the engineering side, Debian and RPM packaging were added (#191), indicating the repo has moved from an operator collection to an installable distribution. Enflame’s core_shapes.yaml had been ineffective for a week—no load point existed in the repo, and benchmarks only recognized a hardcoded kunlunxin branch (#229 added the file, #232 fixed loading); after the fix, lookup was generalized to any vendor and a FileNotFoundError was fixed along the way. On the AMD side, gfx1100 versions of three Mamba operators were added for RDNA3 (#231, 578 lines, bit-identical to the generic kernels).

FlagCX (10 Merges) and the Communication Layer

  • Device layer: Kunlunxin XPU device bitcode build (#676) uses a Makefile to compile the shared device API wrapper into xpu3 LLVM bitcode—extracting the device module from the XDK offload package, retaining public symbols, then optimizing—producing libflagcx_device.bc and consumer-side headers, with communication traits going through XSHMEM. An XPU device IR entry was then added to support FlagTree linking (#678).
  • Semantic fix: Enflame’s Device API gained acquire semantics for Atomic::load (#681, 3 files, +359/−37 lines)—previously load(..., Acquire) and load(..., Relaxed) emitted the same instruction, so observers had no invalidation barrier after seeing a flag; this commit changes it to read-then-fence with scope-selected strength. System scope remains unimplemented because ivcore11 has no corresponding memory barrier instruction.
  • Packaging and adaptation: Tsingmicro TSM support (#674, 10 files, +886/−80 lines) also fixes grouped P2P cleanup, illegal peer rejection, and async stream event handling; AMD adaptation switched to CUDAStreamGuard (#680); Kunlunxin platform traits moved cstddef outside the guard (#682).

Training Stack: FlagTrain (10), FlagScale (2), TransformerEngine-FL (2), Megatron-LM-FL (10 in review)

  • FlagTrain’s style is fixed: A single PR title lists the backend roster directly, and one operator is rolled out across the backend matrix at once. Merged: fused_indices_to_multihot (#29, NVIDIA and Ascend, with H20 benchmarks), baseline comparison mechanism ported (#30, normalizing speed ratios by device bottleneck unit peak scaling factor, output vs Base columns, recording the reason rather than failing when a baseline is missing), multi_tensor_adam (#35, 6 files, +1093 lines, covering NVIDIA, Hygon, MetaX, PPU, and Enflame; a single Triton launch completes multi-tensor Adam updates in batch; on H20, fp32 65536 elements is 2.24× the DeepSpeed CUDA baseline, while the 1024-element small tier is only 0.76×). In review: fused_proj_rms forward/backward (#38), fast_gelu (#33), fp8_gemm (#18), mixed_gemm (#10), and follow-up batches of multi_tensor_adam.
  • FlagScale turns to test discipline: Unified test strategy, affected routes, and execution evidence gates (#1315); offline training operator profiling (#1310, 4 files, +1474 lines)—the training side exports only per-rank Chrome timelines, and an offline extractor performs external ID attribution, communication accounting, and multi-rank aggregation, outputting columnar artifacts consistent with inference profiling. In review: DeepSeek-V4 upstream sync [1/N] (#202) and [2/N] (#211, adding continuous context parallelism for packed sequences), plus lightweight DCP interconversion between HF and MCore (#1319).
  • TransformerEngine-FL two commits: Implemented FlagCICD v1, introducing L0–L4 test tiers and plan-driven execution (#142); rolled back three 3rdparty/ submodules to the upstream v2.17 validation baseline (#150)—previously cutlass had been advanced 240 commits (touching 4,000+ files), cudnn-frontend pushed from v1.25.0 to an unreleased snapshot, and googletest pushed to master HEAD.
  • Megatron-LM-FL deserves a separate note: Ten PRs in review, the first sizable update in nearly two weeks (10-30 window), but no merges this cycle. This training stack stalled after mid-October; whether it has truly resumed pushing needs confirmation next period.

Numerical Libraries, Attention, and New Directions

  • FlagBLAS (2 commits): DAMO XuanTie BLAS1’s fifteen operator groups landed in bulk (#154), followed by L1 naming and reference alignment (#155). BLAS1 is a prerequisite for upper-layer BLAS2, BLAS3, and LAPACK solvers; without this layer, bottom-up self-consistency is impossible—the most easily underestimated commit of the week.
  • FlagAttention (9 commits): Besides PPU’s MiniMax sparse attention (#111), there is Ascend Parallax attention in three stages (#103, 10 files, +2738 lines, covering causal masks, sliding windows, GQA, and variable-length inputs, at 1.0–8.74× FLA on most training shapes), Enflame MiniMax M3 sparse attention prefill and decode optimization (#104, 2 files, +2873/−2516 lines), MetaX C550 Triton fused AttnRes forward (#108, 3 files, +268 lines, from 0.075 ms to 1.496 ms at D=7168 and BF16; the author notes FLA is unavailable so no speedup is claimed), and Hygon removing the FP8 MSA path (#109). Attention-layer fragmentation is worsening, with no cross-vendor unified low-level implementation yet.
  • FlagCV (1 commit) finally clarifies what it is: The first About and README merged (#2), positioning it as “a high-performance computer vision library implemented in Triton,” offering color conversion, filtering, geometric transforms, and arithmetic under OpenCV-shaped interfaces, benchmarked against OpenCV’s CUDA baseline, built on FlagTree with pluggable backends. Timeline: repo created 10-14, skeleton landed 10-18 with operator implementations removed in favor of an immediate-mode skeleton, positioning statement added 10-26—code skeleton first, positioning statement after. There are currently no benchmarks or non-GPU backend data; the real test is memory-bound operator performance on NPUs and DSAs.
  • FlagQAI (4 commits) and its boundary with FlagQuantum still needs clarification: 10-27 saw the first import of a CLI source snapshot, with the first CI round failing at the fixture manifest step (#1 in review); 10-29 added a local quantum workbench web page and native Agent integration (#3), and a fix to retain follow preferences after refresh (#4). The README explicitly lists “synthesizing circuits from intent” as a product direction rather than a completed capability; current verification scope covers only local circuit simulation and one fixed-ansatz two-qubit variational route.
  • Other: FlagDNN’s two commits are both Hygon fixes (GPU name and performance); FlagFFT’s pushes land on the codex/musa-shortfall feature branch, with the default branch’s latest commit still from 10-15; FlagTensor Ascend resident-grid elementwise kernels and vendor tuning (#32, 24 files, +1128/−139 lines); Trident supports Python 3.10 (#5), with the Monad intermediate layer (#4) still in review; flir’s Ascend split and join and static permutation lowering (#86) are in review.

Testing and Release Engineering: optest (12), FlagOps (2), community (5)

  • optest consolidates thirteen vendor scripts into one command: flagos-gpu-check auto-detects in the order “vendor-proprietary device nodes first, SMI commands as secondary confirmation,” preserving each vendor’s original per-card tables, timeouts, and retry parameters, and documents two conflict rules—Hygon before AMD (both have kfd, only Hygon has mkfd) and XuanTie before NVIDIA. Output was then reworked into a single text summary or a single parseable JSON and YAML (19 files, +2947 lines), adding normalized fields such as device, driver, runtime, runtime_version, device_count, and memory_unit, and describing runtime and host driver separately. Enflame S60 was connected to the variant CI of FlagGems-vllm and FlagGems-sglang this cycle.
  • community’s five commits are all rules: Two rewrites of FEP-0140, profiling scope and validation plan, status transition to Implementable, and FEP-0141 narrowing. Clarifications were also written into the body—DeepSeek-V4-Flash and Pro remain initial W8A8 candidates, and “10% throughput improvement over NVIDIA” is an optimization goal, not a fixed acceptance threshold.
  • FlagOps’ two commits are both about stability: Robust detection clears stale git locks left by hard-killed fetches (#18); default connection timeout raised from 30 seconds to 300 seconds (#17).

IV. Member Units and Vendor Adaptation

  • Hygon: One of the vendors with the highest engineering density this cycle. DTK 26.10 completed eight merges in a single day, from containers, availability fixes, the cp312 builder, and the FlagCX wheel line to filling in two soname dependencies, forming a reusable “new SDK onboarding troubleshooting path”; when the container layer first landed, it explicitly stated that “FlagCX has not yet been built, so it is not included at this stage.” Separately, build-infra reissued libglog.so.1 to fix native plugin load failures on DTK images (#1524), Torch-FL fixed the DCU runtime build source (#654), FlagAttention removed the FP8 MSA path (#109), FlagTrain listed Hygon as a first-class backend (#35), and DCU hardware health sampling (FlagScale #1299) and the GLA implementation (FlagAttention #117) are under review.
  • MetaX: Investment concentrated on both operator acceptance and inference performance. The batch submission of PRs for 135 specialized operators was the main reason for the surge in the organization’s under-review count this cycle; the INT8 and FP8 dual paths of grouped_mm_w8a8 are benchmarked against real call replay; on the FlagGems-vllm side, FlashAttention cache safety and graph capture were fixed, TP2/TP4 were optimized, fused MoE tuning was differentiated by stage, and Split-KV scheduling was applied to TP2 packed decode; the full MetaX and MACA backend package for sglang-plugin-FL (31 files, +3364 lines) completed the vendor matrix on the inference framework side. On the ecosystem side, the full-stack adaptation of RLinf was merged into the official mainline (see Section V).
  • Kunlunxin: The earliest to onboard and the broadest in coverage, and therefore also the earliest to enter the long-tail tuning phase. The dozen or so merges this week were almost all about “making existing paths faster and more stable”—scalar chain fusion at roughly 7–10x, contiguous-segment kernels raising the aggregate metrics for batch-norm inference and QKV transformation from 0.228 and 0.260 to 1.357 and 5.062, masked_fill from 0.577 to 0.829, and slice_scatter and vstack rewritten while using sym_numel to recover the vendor operator table that the registration logic had missed. The bitcode build (FlagCX #676) has higher long-term value than any single-operator speedup: it plugs Kunlunxin into the unified device abstraction.
  • Qingwei Intelligent: Synchronized its internal Triton 3.6 development line directly into the open-source backend (27 files, +2264 lines, -407 lines) and tagged a dedicated 3.6 release; TXDA gained graph capture and replay in the vLLM plugin; FlagCX’s TSM support and rpm packaging landed on the same day. The cost is that each sync is large and review must verify item by item against the vendor SDK semantics; the benefit is that the interface contracts of FlagGems and FlagTree can move forward in step with the vendor’s internal progress. On the ecosystem side, promotion of Open3D-PIMC continues (see Section V), but the two lines have not yet converged in code.
  • Huawei Ascend: All four backend keys (cann8.5.0, cann8.5.0-910c, cann9.0.0, cann9.0.0-910c) were brought up to 2.3.0-0.3.0; the compiler moved from being pinned at install time to being forcibly pinned at runtime (#7837), because the image bakes flagtree into /opt/flagtree and the pip pin cannot override it; FlagTree hooked up the TensorView access path (32 files, +4901 lines), selecting between indexed-payload DMA and element-wise copy with zero-padding between CommonIR and HIVM according to the index pattern; FlagAttention added a three-stage implementation of Parallax attention. On the vLLM side, the native decode graph and ModelSlim dynamic W8A8 quantization are still under review.
  • Enflame: Filled in one gap each across the shape table, toolchain, and inference lines. The root cause of core_shapes.yaml having had no effect for a week was that there was no load point in the repo; the fix generalized the lookup to any vendor; FlagPrism’s profiler and debugger were extended to Enflame and enabled by default (#1239, 5 files), with debug-enabled kernel launches routed through the gateway; Qwen3.5 FP8 W8A8 block-calibrated inference landed on GCU (#358, 20 files, +3367 lines), with kernel patches redone around the hardware limitations of GCU300 and GCU400 so that FP8 MoE runs in both eager and full-graph modes. On the review side, a large batch of reference implementation fixes (#7890 through #7908, consecutive numbers) has yet to be closed out.
  • Iluvatar CoreX: Three lines in the convolution family optimized simultaneously—seven condition tiers for conv_transpose2d, removal of channel zero-padding in conv3d, and caching of packed weights plus fusion of the channels_last channel transformation in conv2d; FlagCX added acquire semantics to Atomic::load, which is a communication-correctness issue rather than a performance one. On the hardware side, TianGai 300 was demonstrated live in public for the first time (see Section V); on the software side, adaptation is still being filled in item by item across the Device API, SGLang 0.5.18, and training operators.
  • DAMO XuanTie: Maintained a “one whole block at a time” cadence for three consecutive windows—inference (Zhenwu Express edition and PPU sparse MLA forward), attention (MiniMax sparse attention on PPU, geometric mean 1.800x), and the numerical library (fifteen BLAS1 operator groups). In addition, fused_q_kv_rmsnorm landed on the platform on 10-29, both multi_tensor_adam and fp8_gemm in FlagTrain list it as one of the backends, and optest’s vendor conflict rules rank it ahead of NVIDIA. Next to watch is whether BLAS2 and BLAS3 follow, and whether the CPU side and the accelerator-card side share the same set of check scripts.
  • Moore Threads: The focus of investment is the compiler rather than operator count. Merging resident GEMM and SPMC into a single superset (63 files, +6192 lines, -403 lines) is the prerequisite for backbone operators such as addmm, baddbmm, and bmm to reach usable performance on MUSA; this capability is also reused by the TLE lines of Ascend and MetaX; the SDK was upgraded to v0.7.1 to align with the dedicated 3.6 tag. On the ecosystem side, Megatron-MUSA-Titan was open-sourced (see Section V); its intersection with this stack remains at the operator and plugin layer rather than the training framework layer.
  • Horizon Robotics: The only onboarding this week that turned a “new platform from unusable to usable” (Torch-FL #674). The value lies in opening up the path rather than in performance—40 element-wise operators are the starting point, while backbone operators such as convolution still rely on whole-graph compilation; the author also recorded two negative findings: libhbtl.so is only a CPU reference implementation, and dynamic shapes are not executable on HBRT 4.7.5 (the loader declares that axis as stride 0, and task validation requires no less than 64).
  • Cambricon: No dedicated repository pushes or merges within the organization this cycle, leaving only two traces in build-infra—changelog bookkeeping for two neuware versions (4.4.3 and 4.7.2), and the withdrawal of two megatron images that were never pushed. The previous weekly report already flagged this vendor as a gap, and this cycle continues that; we recommend listing it separately as a risk item in the next issue.
  • Sunrise: tangrt1.2.0 entered the application image matrix for the first time, and libflagcx-sunrise entered the rpm line (the SDK lands in /usr/local via tangtk --toolkit and pccl); the vLLM 0.28 runtime adaptation and the shared Gate CI are still under review (#647).
  • AMD (new backend): This cycle it grew from a single base image into a complete backend, with all five steps in place: configuration, packaging, wheel line, runtime verification, and builder catch-up; SGLang ran tensor parallelism on the R9700. On the FlagGems side there is still no HIP C++ backend, and its vendor descriptor has the problem of setting the device name to cuda (fix under review, #7908), indicating that the AMD line is still primarily on the Triton path.
  • SpacemiT, this chip vendor, and ARM: SpacemiT’s vmt4d backend in FlagTree is still under review (#1455), the only RISC-V AI action this week; on-device coverage for MiniCPM-OCR brought in this chip vendor and Mac (ARM), with the main linear layers accelerated by SME2 matrix instructions on the M5 CPU and operators connected to the execution path via Triton TLE Raw, averaging 1.2 seconds per page-block discrimination.

V. Ecosystem and Community

  • InfoQ publishes the most complete Chinese technical retrospective since 2.2 (10-24): As of Q3, the FlagOS ecosystem has 107 member organizations, 464,336 community downloads for the quarter (4.76x Q2), and 264 code contributors (up 55% from the previous release); from 2.1 to 2.2, merged PRs rose from 1,890 to 4,890, code commits from 5,100 to 9,730, and new Issues from 420 to 1,423; the nine operator libraries total 1,454 operators, up 890 from the previous release, with overall cross-chip performance improving about 27% across over a thousand operators and 10 chips; GLM-5.3-Flash on existing Ascend 910B raised logical service throughput from 8.52k to 17.36k tokens/s (2.04x), with 512K long-context generation at 60.9 tokens/s. The cost figures are calculated on the basis of RMB 16,500 per month for an 8-card 910B machine, 3P1D deployment, and a 93% cache hit rate: in the 256K input, 8-concurrency scenario, the cost per million output tokens works out to RMB 59.27, and in the 512K input, 4-concurrency scenario, RMB 104.53—19.4% and 27.6% lower than the corresponding commercial APIs, respectively. These are rental-cost-derived estimates, not measured comparisons under identical workloads, and this caveat should be retained when citing them.
  • The MiniCPM-OCR adaptation note states three types of numbers separately (10-29): The actual throughput ratio (Jev reaches 98.7% of Nvidia H100 native on DAMO XuanTie), the throughput ratio normalized by peak compute (OCR 1.0 single-document P50 169.3%, batch 137.1%), and on-device latency (M5 CPU average 1.2 seconds, median 895 milliseconds) are each annotated with their premises, and it explicitly states that the 169.3% figure holds because low-peak-compute platforms achieve higher utilization, not because a single card is faster. This is the first recent material from this stack to state “catching up to native” and “higher utilization” separately, which is more informative than a single multiplier.
  • Community content shifts from launch-event-style presentations to single-point technical livestreams broken down by plugin (10-29): A session starting at 19:00 took cross-chip inference adaptation of sglang-plugin-FL as its topic, covering ATen operator replacement, fused operator scheduling, unified communication abstraction, KV Cache transfer under PD disaggregation, and dependency splitting in Empty mode; it states that adaptation has been completed for ten chip platforms including Ascend, Hygon, and Kunlunxin. This is consistent with progress on the code side (the repo saw 6 PR updates under review this week, including 0.5.18 Empty runtime adaptation for Ascend and Tianshu). This session, together with the 10-22 university roundtable and the 10-15 operator bounty challenge, forms a continuous line of technical outreach.
  • Qingwei takes Open3D-PIMC from open-source debut to teacher-training classrooms in thirty countries (10-26): The project, jointly developed by Qingwei Intelligent and Beijing Academy of Artificial Intelligence, is a programming model and open-source software framework for 3D compute chips. It was officially open-sourced at the China Computing Conference in September and positioned as one of the main Zhongzhi FlagOS solutions for next-generation 3D chips; developers describe only data distribution and task partitioning, and the framework automatically handles the partitioning and invocation of graph compilation and just-in-time execution. On the inference side it natively connects to vLLM and SGLang, with each vendor’s private instruction set and microarchitecture capabilities integrated as plugins. This report focuses on ecosystem promotion rather than code: the Global AI Open Computing Teacher Development Program brings Qingwei engineers into the classroom, with trainees being nearly fifty university core faculty from more than thirty countries. The statement that it “has been adapted to 20 chip vendors and over 30 AI chips” is the reporting party’s figure and is not fully consistent with the official figures of 21 vendors and 35 chips given at the October Open Computing Conference; attribution should be distinguished when citing.
  • MetaX brings an embodied-intelligence reinforcement learning framework into the upstream mainline (10-26): RLinf was launched by Tsinghua University and Infinigence AI together with Beijing Zhongguancun Academy and other institutions, positioned as the first large-scale reinforcement learning framework for embodied intelligence integrating simulation, training, and inference, with results accepted at OSDI, RSS, NeurIPS, and other conferences. MetaX completed two tiers of SFT—512 cards and 1024 cards (128 nodes x 8 cards)—on a cluster of XiYun C-series GPUs, training the Pi0.5 model on the RoboTwin dataset; success rates on all four task groups matched or exceeded the values reported in the paper, with one group 8.8 percentage points higher, and multi-machine scaling linearity remained above 97%. Integration follows a four-layer plugin alignment (a new device manager added to the accelerator abstraction layer and registered in the RLinf registry; environment variables controlling multi-card visibility and coordinating with Ray scheduling; communication defaulting to MCCL; and a software stack based on MXMACA’s PyTorch and FlashAttention supporting BF16 and FSDP). This is not a FlagOS component release, but the direction is worth noting—it overlaps with FlagOS-Robo and FlagScale in scenario, and whether a relay emerges in which “member organizations first merge into upstream frameworks, and FlagOS then consolidates a unified backend” is a thread worth following.
  • Moore Threads open-sources training infrastructure; code and narrative should be viewed separately (10-28): Megatron-MUSA-Titan targets trillion-parameter MoE training on ten-thousand-card clusters, covering pretraining and reinforcement learning, supporting blockwise FP8, combining DeepEP with ACE asynchronous communication for expert parallelism and compute overlap, and working with slime and miles (Megatron training plus SGLang sampling). The repository exists but saw no pushes within this window, with the last push on 10-16—this is a case of “announced as open source, code unchanged,” and the “open source” wording in the press release should be viewed separately in terms of timing. Also released the same day was the Q3 report (revenue of RMB 1.55 billion, up 1773.9% year on year; revenue of RMB 3.289 billion for the first three quarters, net profit attributable to shareholders of RMB 37.6973 million; and progress toward a secondary listing in Hong Kong). The financial report does not change the technical judgment, but it explains the company’s capacity to invest in its open-source cadence.
  • Tianshu Tiangan 300 makes its first live demonstration, but the hardware claims still lack verifiable conditions (10-28): At a media open day in Shanghai, the company demonstrated the Tiangan 300 general-purpose GPU live for the first time, calling it the first domestic general-purpose GPU whose measured performance reaches the level of Nvidia’s H200, with third-party testing converting to an overall single-card throughput 1.05x that of H200, and surpassing H200 on complex multimodal tasks such as text-to-image and text-to-video. This figure is the company’s own claim; the test methodology, models used, and workload conditions were not disclosed and cannot be verified. Corresponding moves on the software stack side are ongoing—FlagCX adds Device API retrieval semantics, SGLang 0.5.18’s Empty runtime adaptation is under review, and multi_tensor_adam has listed Tianshu as a supported backend.
  • Channel check: for four consecutive windows, the news surface contains only member-organization press releases (10-23 to 10-29). Across five daily briefs, 120 Chinese and English queries were run (24 per issue), and direct queries for component names (FlagOS, FlagGems, FlagScale, FlagTree, FlagPerf, FlagCX, KernelGen) continued to yield zero hits in both Chinese and English combined. The five issues yielded eight valid items in total: six from Google News—InfoQ’s 2.2 retrospective (10-24), the MetaX and Moore Threads MiniMax M3.1 Flash Day-0 press releases (10-23), Qingwei Open3D-PIMC (10-26), MetaX RLinf (10-26), and Moore Threads Megatron-MUSA-Titan (10-28); and two from the community’s own channels—the MiniCPM-OCR dual-model Day0 adaptation article (10-29 11:19) and the sglang-plugin-FL technical livestream (10-29 19:00). The CSDN FlagOS column, after stopping updates on 10-22, resumed on 10-29; eight HN Algolia queries over a four-day window produced zero direct hits; the BAAI community search page is client-rendered, yielding only the framework page; a seven-day inspection of the official websites of eight member organizations produced only four items (Moore Threads’ 4K post-production network and Q3 report infographic, MetaX’s CNCC 2026 sub-forum recap, and one industry-deployment piece unrelated to the software stack); and the pending-inclusion queue had no FlagOS entries this cycle.

VI. Trend Observations

  • The bottleneck for 2.3 is no longer code, but whether the release can self-verify: The densest batch of work this cycle was not new operators, but gates, audit trails, retractions, and consistency checks—the changelog went from “human memory” to a push gate, published to the site page and Harbor; the application-page consistency check was wired into pre-commit; and two never-pushed images were retracted so that “the changelog file set equals the published set.” These actions produce no capability, but they directly determine whether the release manifest before 12-30 can be externally verified. The current state is that the build side is already accounting against 2.3.0 while the release manifest remains empty; the 11-13 FEP deadline and the 11-30 rc0 will compress the entire rc period.
  • The backend matrix continues to expand rather than converge in the 2.3 cycle: AMD ROCm 7.2.4 grew from a base image into a full backend, and the Horizon BPU went from “cannot be eager by design” to per-operator execution. What these two share is that the follow-up work required “only after integration” is extremely heavy—AMD needs builders and wheel rows added, the BPU needs distribution logs, copy-kernel guards, and vendor-name mapping, and the first hurdle for a new backend is always “it runs” rather than “it’s faster.”
  • Day-0 delivery has moved from “can it run” to “batch replication in a unified format,” and the next deciding factor is the measurement basis: Two nine-chip simultaneous releases within a week, with this round converging on a single W8A8 path and making four vendors Express editions, shows the release pipeline has been templated. The MiniCPM-OCR note goes further, stating the actual throughput ratio, the peak-normalized throughput ratio, and the on-device latency separately with explicit preconditions—this is more informative than a single multiplier and easier for peers to compare on the same basis in the next round.
  • With operator supply automated, all human effort shifts to correctness and contracts: KernelGen generating 22 operators in a single day and multiple batches per week has become the norm; by contrast, the most valuable commits this week were issues that “don’t error in tests but blow up in production”—int32 offset overflow in index_put, the Tianshu bf16 GEMM falling back to host, the Hygon DCU runtime linked from stubs, the missing shape-table load point in Enflame, and the Kunlunxin backend failing to import. The landing of ref-as-candidate in both repos plus 57 test fixes is the watershed that changes “what to test” from whether an operator exists to whether the reference and implementation agree.
  • The cost of rule convergence is deferred and comes due on 0.32: Skipping 0.28 appears to have eliminated the cost of chasing minor versions, but the adaptations already merged on 0.28 (Enflame S60, Tianshu, MetaX, Tsingmicro, Kunlunxin) need to go through acceptance again on 0.32, and no PR currently carries this rework. The first landing evidence for 0.32 in the same period is the native CUDA vLLM 0.32 adaptation (pinning vLLM 0.32.0 with cu129, PyTorch 2.13.0, Python 3.12.3); domestic backends have not yet begun.
  • The quantum stack has fully decoupled from multi-chip adaptation and become an independent mainline: FlagQuantum merged 226 commits in a week, accounting for 30% of the organization, and moved from structural reorganization (QEC package split, hard switch of the Quafu SDK) to scenario expansion (error-correcting codes, neutral atoms, thermal baths), then converged on the CS-01 to CS-07 circuit synthesis pipeline; FlagQAI built a local workbench in parallel. Its way of working is four-stage evidence retention—high cost, good verifiability—and it is the only software-stack mainline that does not depend on any chip vendor’s progress.
  • Three risk items need confirmation in the next issue: First, tags lacking release notes has become customary—FlagCX v0.14.1 and both FlagTree 3.6 special releases have only tags, forcing downstream to infer the backend and Triton version from the name; if 2.3 is delivered this way, verification costs will rise. Second, Cambricon has had no dedicated push within the organization for two consecutive weeks, leaving only a retraction record in build-infra; if this continues next issue, it should be listed separately. Third, the recovery of the training stack remains uncertain—Megatron-LM-FL has ten commits under review but zero merges this cycle, and FlagScale’s DeepSeek-V4 upstream sync has only reached [2/N]; training-side progress lags behind inference.
  • Next observation points: When the 2.3.0 tag is cut and when release-2.3.yaml is created; under the single-release 0.32 rule, when the first domestic backend (Ascend or Hygon) completes acceptance on 0.32; whether the BPU path expands from elementwise operators to backbone operators such as convolution; when FlagCV provides its first set of benchmarks and non-GPU backend data; and whether Megatron-MUSA-Titan code actually starts being pushed and forms reuse with Megatron-LM-FL.

Appendix: Sources and Verification

  • Sources: Five FlagOS daily reports dated 2026-10-26, 10-27, 10-28, 10-29, and 10-30, with windows of 10-23 06:00 to 10-26 06:00 (72 hours), 10-26 06:00 to 10-27 06:00, 10-27 06:00 to 10-28 06:00, 10-28 06:00 to 10-29 06:00, and 10-29 06:00 to 10-30 06:00 respectively; no issues were missed during the period. 10-24 and 10-25 were weekend days with no standalone daily report; their content is included in the 72-hour window of the 10-26 issue.
  • GitHub verification method: Push status was checked day by day for all 61 repositories in the flagos-ai organization; merges were verified using is:merged plus merged:>=window start as the source of truth, and in-review items using is:open plus updated:>=window start; new commits on the main branch were re-checked with commits?sha=<branch>&since=<UTC>; pushes to non-default branches were identified via the org event stream and commits.atom as a fallback (this period involved repos including docs, release-info, FlagFFT, FlagSparse, FlagGems-Experimental, and TransformerEngine-FL). Per-repo merge counts are the sum of the figures disclosed in each daily report; the per-repo totals for each issue match the total merge count for that issue exactly, for a cumulative total of 755.
  • Version and tag verification: Each component repository’s tags and Release atom feeds were checked one by one. The 10-31 verification results are as follows: FlagTree 0.7.1a1+mthreads3.6 has a tagger time of 10-26 10:13, and 0.7.1a1+tsingmicro3.6 of 10-29 11:09; neither has Release body text. FlagCX v0.14.1 is a lightweight tag pointing to the merge commit of 10-29 10:55 (Kunlunxin cstddef backport); the most recent entry in the Releases list remains v0.14.0 from 9-28. The latest tag in the build-infra tag list remains v2.2.0; the community repo’s release/2.3 directory contains no release-2.3.yaml. FlagGems, FlagQuantum, FlagScale, FlagBLAS, FlagDNN, FlagFFT, FlagTensor, FlagAttention, vllm-plugin-FL, sglang-plugin-FL, FlagGems-sglang, and TransformerEngine-FL had no new Releases this period.
  • News-side verification: 24 sets of Chinese and English Google News RSS queries (14 days for component names, 7 days for member and industry terms) were run for each issue, totaling 120 queries across the five issues; eight sets of HN Algolia queries; item-by-item time verification of the CSDN FlagOS column; daily inspection of the BAAI community and the official websites of the eight member companies. Valid items are cited with “original site first”; reposted old news (Suiyuan-style “listed today” articles; the company’s STAR Market listing date was 9-11), out-of-window articles (the original Tsingmicro “Annual Sci-Tech Innovation Pioneer” article was dated 10-22), post-event coverage (Huixi Intelligence attendance articles pointing to the 10-17 to 10-18 conference), and market and earnings articles were excluded per the rules and not counted as items.
  • Scope notes: All dates and times are Beijing time. The Monday 72-hour window covers the 10-24 and 10-25 weekend; its content is labeled by original date and overlaps with the previous weekly report (covering 10-19 to 10-23) on 10-23. The tags and merges in the overlapping portion were already listed in the previous issue and are not counted again here. “Merge” refers to PRs whose GitHub merge time falls within the window; this differs by about one day from the daily reports’ day-by-day window counts, and this report uniformly adopts the merge-date basis. Commit searches use search’s total_count basis; for a few repositories, compressed merges and indexing delays can cause the merge count to exceed the commit search count (e.g., the 10-27 issue’s FlagGems shows 49 merges versus 28 commits), and the report uses the merge count as authoritative. Vendor press-release phrasing such as “Day-0,” “no code changes required,” and “matches or exceeds the paper” reflects company claims and has not been independently reproduced; the Tiangai 300’s 1.05x H200 claim and InfoQ’s cost estimates are both noted with their qualifying conditions.
  • Limitations: Branch-level activity (FlagTree’s triton_v3.5.x and feature/flagmega branches, FlagGems’ kernelgen-dev and fix/* temporary branches, FlagFFT’s codex/musa-shortfall) cannot be fully enumerated on a default-branch basis; default-branch statistics underestimate actual work. FlagQuantum’s commit count includes merge commits and branch-sync commits and is not equivalent to the number of functional changes. As of the end of this period, all 135 batched PRs in FlagGems-Experimental remain in review; whether they will be merged in bulk and whether the merged operators will flow back into the main repo’s operator table remains to be seen. On the training side, Megatron-LM-FL and FlagScale show sparse activity, so confidence in related judgments is lower than for the inference stack.

References