FlagOS Weekly Report (2026-11-02 ~ 2026-11-06)

Reporting period: Monday, November 2, 2026 through Friday, November 6, 2026 — 5 working days in total.

Sources: 5 issues of this publication’s daily FlagOS update reports (11-02 / 11-03 / 11-04 / 11-05 / 11-06; no issues missing within the period). The 11-02 issue is the Monday morning report, whose research window starts from the previous issue’s cutoff at 10-30 06:00 — a 72-hour window covering the weekend of 10-31 and 11-01; the four issues from 11-03 to 11-06 use 24-hour windows that run back-to-back, with the final window spanning 11-05 06:00 to 11-06 06:00. Accordingly, the factual interval of this report is 10-30 to 11-05, with the 10-30 to 11-01 portion labeled by its original dates.

Editorial note: Organized across six dimensions: top stories of the week, versions and releases, component and code co-building, member organizations and vendor enablement, ecosystem and community, and trend observations. Summed across their respective windows, the five daily reports total 1,117 commits and 715 merges; counting only the four complete 24-hour windows (11-03 to 11-06), the totals are 861 commits and 600 merges. The number of repositories with pushes per issue was 17, 16, 24, 26, and 21 respectively, out of 61 organization repositories in total. Versions and tags were independently re-verified against the tags and Release atoms of each component repository; no new Release objects were created during the period.

I. Weekly Highlights

Within a week, the 2.3.0 image layer expanded from four tiers to six; all 23 base and 23 runtime images are now tagged 2.3.0, yet the release manifest still contains only the schedule table (10-31 to 11-05): New coverage includes Hygon DTK 26.10 base and runtime, AMD ROCm 7.2.4 runtime and the FlagTree amd build line, Ascend CANN 9.2.1 base (only 910B, python 3.12, torch 2.13, triton_ascend 3.6.0, with FlagTree and FlagCX deliberately left empty), and NVIDIA cuda13.3 (torch 2.13.0+cu130, triton 3.7.1, while cuda12.8 is frozen with enabled set to false). The release/2.3 directory in the community repo contains only the Chinese and English schedule tables, and release-2.3.yaml is still 404; the atomic check of Releases across 31 repos and Tags across 8 repos showed zero additions all week. Per the schedule, 11-13 is the FEP merge deadline, 11-30 is feature freeze with rc0 cut, 12-07 is rc1, 12-14 is rc2, 12-25 is final freeze, and 12-30 is GA.
vLLM 0.28.0 was closed out by four backends within a single day, and the next day a repack rolled it out to 11 vendor indexes (11-03 to 11-04): Tsingmicro TXDA implements eager only and actively rejects graph mode (#642, +3067/−146, 29 files); MetaX C550 does a “0.28-empty” stub adaptation despite no corresponding upstream branch (#554, +2838/−70, 36 files); Moore Threads MUSA brings in native MCCL and segmented native graphs in one go (#575, +7804/−233, 46 files); Ascend builds a FULL_DECODE_ONLY decode-specific graph (#646, +3342/−340, 39 files). The four together total +17051/−789 across 150 files. On 11-04, build-infra #1635 writes vLLM 0.28.0+flagos into 11 indexes (AMD, Ascend, Cambricon, Enflame, Hygon, Iluvatar, Kunlunxin, MetaX, NVIDIA, Sunrise, Tsingmicro), with cp311 and cp312 for aarch64 and cp310 and cp312 for x86_64.
Cambricon MLU enters Torch-FL as a native platform; the next day fused attention forward/backward is filled in and CPU fallbacks in a Qwen3 training step drop from 190 to zero (11-04 to 11-05): #720, +4870/−64 across 40 files, writes cambricon into flagos_platforms.json and fills in the libcnrt runtime layer, the torch.mlu shim, backends_cambricon.conf, CI configuration, and the platform contract; the whole stack runs on stock torch 2.10.0+cpu, without torch_mlu, without FlagTree, and without a CUDA runtime, and was tested end to end on eight MLU590-M9 cards. The next day, #748 and #749 wire CNNL fused attention forward and backward back into SDPA coverage and wrap them as a C++ autograd Function; #757 runs a fallback census on a full Qwen3 causal language model training step, finding that of 190 cpu_fallback calls, 188 come from aten::mul.out and 2 from aten::embedding_dense_backward; after routing them through CNNL on MLU, the step reports zero fallbacks. On the same day, #724 removes the cambricon CI lane on the grounds that no runner can host it.
DAMO XuanTie merges 13 specialized operators in batch form within a single day while bumping the ZW810E cost model to 1.1.0 (11-02): FlagGems merges 13 PRs in the 43 minutes from 16:03 to 16:46, all tagged as KernelGen XuanTie output, covering long-tail items such as Chebyshev polynomials, igamma, 3D convolution and transposed convolution, quantized LSTM, fused RMSNorm backward, matrix norms, 3D adaptive pooling backward, and Lanczos upsampling—23.6% of FlagGems’ 55 merges that day. FlagTree #1236 bumps the ZW810E MM/MV cost model package to 1.1.0, with 8 BF16 mm variants and 2 mul models, and makes the tuning contract accept an ordered configs list. On 11-05, FlagAttention #127 opens another Wall Attention optimization ticket for PPU-ZW810E.
The quantum stack turns “hardware acceptance + resource accounting” into regressible evidence: the Ascend 910C native provider passes 167 items, and the synthesis line advances to UP-06 within the week (10-31 to 11-05): FlagQuantum #958 moves the 910C from experimental split-FP32 to the native provider operator path; the PR body records 167 passed in 115.41s (142 circuit, noise, TEBD, and QEC cases, plus 25 native dynamics cases, including two cold-process plan replays), with 1332 passed on the CPU-side regression; #970 adds a fail-closed native regression lane on pre-provisioned ARM64 runners. Over the week the synthesis line advances from UP-01 (Python qfunc frontend), AO-00/01/02 (arithmetic baseline, normalization, protected arithmetic), and PF-00/01 (compile latency and RSS accounting) to UP-04/05/06 (bounded uniform state preparation, scalar coherent control, U gate and array Hadamard). On 11-05, the fault-tolerant compilation integration PR #1084 was opened as a draft, with 276 files and +31011 lines.
FlagGems converges cross-backend evaluation onto “one ruler” and completes backend key versioning the same week (11-03 / 11-05): At 16:41 and 16:42 on 11-03, 23 PRs merge within two minutes, 21 of them from the same author, migrating the H800 reference reads for four operator classes—attention and pooling, reduction and linear algebra, pointwise, and sparse and tensor layout—from scattered readers to unified JSON; previously the source, units, and rounding conventions of reference values were scattered across the code, leaving cross-backend scores without a common baseline. On 11-05, #8446 changes the seven bare vendor names in backends.yaml to version keys consistent with pyproject.toml (hygon-dtk2604, iluvatar-corex450, kunlunxin-xre5371, spacemit-xxx, sunrise-tangrt120, thead-ppu210, tsingmicro-tsm260610), fixing the issue where uv pip install ".[tsingmicro]" silently matched no extra, causing neither torch nor FlagTree to be installed.
Community governance: seven FEPs enter review within an hour, turning 2.3’s multi-backend capabilities into acceptance items (11-05): From 08:29 to 09:31, seven single-file FEPs, all in Provisional Draft status and all from the same submitter. The list is FEP-0163 FlagMega v0.1, FEP-0164 TLE distributed fusion and auto-tuning, FEP-0165 TLE Raw five backends, FEP-0166 FLIR Ascend and GPGPU optimization, FEP-0167 twenty operator–device pairs, FEP-0168 FlagTree multi-platform and Triton API compatibility, and FEP-0170 FlagPrism v0.2. The most substantive, FEP-0163, maps five objectives to acceptance evidence, including GLM5.3 Flash decode throughput on four H800 cards exceeding vLLM by more than 5%, while explicitly noting that CoreX 5.0, the release matrix, and checkpoint reproduction remain outstanding. All seven bodies state “no GPU or model acceptance run performed,” separating scope claims from completion claims.
Industry side: FlagOS 2.2 cases begin to show quantifiable gains, and the edge-side narrative is filled in the same week (11-05): Two CSDN columns. China Telecom’s Xingchen Xing4.0-29B-A4B mHC multi-channel residual operator cuts cluster slowdown on Ascend 910C from 25% to 12%, with the adaptation already merged into MindFormers; after rewriting 12 long-sequence operators for the Agent scenario, first-token latency drops 19.87%; iSoftStone brings GLM-5.2 single-token latency on four 910C machines from 17.79 ms down under the 16.13 ms admission line. A set of 2.2 totals: 1454 operators across nine operator libraries, FlagTree covering 20 vendor backends, 27.6% overall performance improvement on 10 chips, Day0 adaptation for 12 chips, 107 community members, and 460,000 quarterly downloads (4.76× the previous quarter). The edge-side session gives adaptation statistics for 21 vendors and 35 chips, with measured gains of 21%–25% for MiniCPM and Qwen running on pure ARM CPUs.

II. Versions and Release Activity

2.3.0: All six image layers now have changelog entries, but the release manifest still only contains the schedule

Image layer	Landing date	Key content
base and runtime: hygon-dtk26.10	10-31 ~ 11-04	The base image installs ROCm-aware Open MPI; the runtime adds the Hygon DTK 26.10 build of flagcx 0.14.1, with python 3.12 paired with the torch closure for DTK 26.10; after the vendor triton is upgraded to 3.7.0+dtk2610, only the hcu driver is active, fixing the issue where serve fell back to the V1 model runner
runtime: amd-rocm7.2.4	10-31 ~ 11-02	flagcx pinned, amdsmi added, invalid device-visibility environment variables removed, torch closure aligned with vLLM 0.32; a separate FlagTree amd packaging line is created for provenance and A/B reconciliation
base: ascend-cann9.2.1	11-03 ~ 11-04	Only 910B, python 3.12, torch 2.13, triton_ascend 3.6.0; because there is no CANN 9.2.x version pin, FlagTree and FlagCX are deliberately left empty; the first build lacked the OCI provenance label, and the label was added and the image re-pushed on 11-04
base and runtime: nvidia-cuda13.3	11-05	torch 2.13.0+cu130, torchvision 0.28.0+cu130, triton 3.7.1; torchaudio 2.11.0 and FlagTree 0.7.0 are decoupled from torch; cuda12.8 is frozen because torch 2.13 no longer ships cu128 wheels

Coverage: As of 11-05, the changelogs of 23 base and 23 runtime images all record 2.3.0, covering 23 toolchain lines from 12 vendors, including AMD ROCm 7.2.4, Ascend CANN 8.5.0 and 9.0.0 (including the 910C variant) and 9.2.1, Cambricon neuware 4.4.3 and 4.7.2, Enflame tops 1.9.10 and 1.10.6, Hygon DTK 26.04 and 26.10, Iluvatar corex 4.4.0 and 4.5.0, Kunlunxin XRE 5.37.1, MetaX MACA 3.7.2.1 and 3.8.1.3, Moore Threads MUSA 4.3.6 and 5.2.0, NVIDIA CUDA 12.8 and 13.3, Xiwang 1.2.0, and Tsingmicro tsm260610.
Why the Ascend base uses python 3.12: Two hard constraints are stated in the PR description—on flagos-pypi-ascend, the wheels for torch 2.13, torch-npu 2.13, torchvision 0.28, and torchaudio 2.11 are only available for cp312; CANN’s set_env.sh injects its bundled python tree into PYTHONPATH, so the base interpreter must exactly match the runtime venv, otherwise imports will mix versions. numpy is also pinned to 1.26.4.
Why the base deliberately omits FlagTree: 9.2.1 has neither a corresponding flagtree version pin nor a corresponding flagcx wheel, so this layer leaves flagtree, flagcx, and their dependencies all empty; the build order is changed to base, runtime without FlagTree, FlagTree builder, FlagTree wheel, and runtime refresh; when flagtree is absent, the compiler falls back to triton.
Retirement mechanism: The freeze of cuda12.8 is not a deletion—an enabled field is added to configs.yaml and set to false; the specs, images, and documentation are all retained, and the image stays on the flat tag from its last build; the script backend_enabled.py becomes the sole resolver, shared by generate_matrix.py, the two status reports, and the flagcx and vllm-plugin registries, so the frozen state cannot enter any build matrix.
Release status: The community release/2.3 directory currently contains only the release schedule; the manifest file is planned to be generated at the 11-30 feature freeze. According to the 2.3 schedule, the FEP merge deadline is 11-13, feature freeze is 11-30 with rc0 pulled, rc1 is 12-07, rc2 is 12-14, final freeze is 12-25, and GA is 12-30. Images running ahead of the manifest is within the planned cadence; 11-13 is the hard boundary for this version’s scope.

This week’s tags and Release manifest: zero additions, FlagCX v0.14.1 still only a tag

Zero additions: Across five daily reports, the Release atom sources of 31 repositories and the Tag atom sources of 8 repositories were checked day by day, and there were no new Release objects all week. The only update with a timestamp is the FlagCX v0.14.1 tag (refreshed at 11-01 00:10), while the latest official release on GitHub Releases remains v0.14.0, published on 2026-09-28, whose body states it corresponds to FlagOS 2.2.
Component version lines unchanged: The FlagGems official line remains 5.4.0; 5.5.0.dev0 has had no new tags since the line opened on 10-12; FlagQuantum uses v0.3.1 as the quantum stack baseline; FlagScale, FlagBLAS, FlagDNN, FlagFFT, FlagTensor, FlagAttention, vllm-plugin-FL, sglang-plugin-FL, and others remain at the 09-28 batch.
Assessment: This is a typical lull after the 2.2 release and before 2.3 reaches GA on 12-30—external versions are quiet while the artifact and build lines are active. Compared with last week, the only change is that image-layer coverage has expanded from four layers to six; the tag and manifest steps are still absent.

vLLM plugin: 0.28 closes on four backends on the same day, repack rolled out to 11 indexes

Four landing strategies: For the same upstream version, each of the four backends chooses its path according to its own conditions. Tsingmicro removes TXDA’s graph capture and partitioning implementation, directly rejects graph and compilation configurations at the configuration stage, and prompts for –enforce-eager; the rationale is that the segmented original graph has passed gating for two models under TP8, but Dense TP1 correctness has never been resolved. MetaX keeps all changes within vllm_fl and CI scripts, gating by vendor name or runtime detection; review explicitly rejected the approach of writing a .pth startup hook into site-packages. Moore Threads brings in native MCCL, FX/eager compilation, and segmented native graphs all at once, with graph handling consolidated into a single graph.py. Ascend implements only FULL_DECODE_ONLY decode graphs, leaving prefill, vision encoding, and sampling outside the graph.
repack mechanism: build-infra’s mechanism of “release steps write the directory, humans only write the copy” was formally put into operation this round, replacing the previous manual editing of the pypi_index field; one boundary fix splits the vendor at the first hyphen, avoiding truncating the platform name incorrectly when the version string contains both a + platform segment and a - segment. On the same day, a daily wheel line was added for FlagGems-vllm, the build and upload containers pass through the proxy, and the Ascend verify container was given an additional 1 GB /dev/shm.
0.32 line in parallel: While 0.28 closes, five adaptations for 0.32 are advancing in the review queue—Enflame S60 (#675), Iluvatar (#674), AMD ROCm gfx1100 (#659), MetaX C550 (#693), and unified FL execution plus Enflame adaptation (#667). Running the maintenance line and the target line simultaneously has become the norm, and vendors need to maintain two sets of validation environments.
Sync mechanism: Four forward-syncs from 0.4.0-dev to 0.5.0-dev were merged this week (#676, #678, #688, #689); the method changed from whole-branch merges to replaying reviewed increments while preserving source commits, with conflicts disclosed via draft PRs; on 11-05, #698 completed another forward sync.

Community governance: seven FEPs and the 2.3 scope statement

List and positioning: FEP-0163 FlagMega v0.1 targets model compilation, vLLM integration, and multi-card decoding; FEP-0164 targets TLE distributed fusion and auto-tuning; FEP-0165 makes TLE Raw cover five accelerator backends; FEP-0166 is FLIR optimization for Ascend and GPGPU; FEP-0167 focuses on compiler optimization for twenty operator—device pairs; FEP-0168 is FlagTree multi-platform support and Triton API compatibility; FEP-0170 is multi-backend debugging and profiling for FlagPrism v0.2.
Common wording: All seven bodies state “no GPU or model acceptance was run,” separating the scope statement from the completion statement; the community repo also has four codex/fep23-* branches pushed within the window, showing that FEP drafting and branch preparation are the same pipeline. This batch appeared eight days before the FEP merge deadline, right in the window for scope additions.

III. Components and Code Co-building

FlagGems: Five Batches in One Week, Shifting from Coverage to Comparability and Backend-Specific Implementations

Scale: Across the five daily-report windows, merged PRs numbered 55, 76, 35, 33, and 33 respectively, totaling 232 — the largest single-repo merge volume in the entire organization. The 76 merges on 11-03 were the weekly peak, accounting for 42.9% of the organization’s 177 merges that day.
XuanTie batch: The 13 merges on 11-02 concentrated on long-tail entries, including Chebyshev polynomials, igamma, 3D convolution and transposed convolution, quantized LSTM, RMSNorm backward fusion, matrix norms, 3D adaptive pooling backward, and Lanczos upsampling. These operators previously had low returns under generic Triton implementations; after specialization they can go directly into default dispatch. There is currently no record of integration with the FlagGems-vllm inference path.
Kunlunxin contracts and tuning: #8038 on 11-02 fixed a silent bug — the fast path for foreach-series out-of-place scalar overloads compared only element counts, not shapes, so lists with different shapes but equal element counts would all inherit the first tensor’s shape; the fix gates admission on full shape, and two other PRs changed sixteen scalar outputs to single-base-address addressing and merged list outputs into a flat buffer. On the same side, #8034 evaluates the autotuning grid before submitting JIT, and #7976 changes slot retrieval to use program_id(0); on the performance side, a dozen or so PRs cover pointwise fast paths, pool3d backward fusion, Chebyshev expansion, Jacobi blocking, and a single-formula linspace. #8123 reverted a BF16 pointwise optimization and #8245 redid it with a different approach — one revert and one replacement show this path is still being iterated.
Iluvatar and NVIDIA: Between 16:04 and 16:10 on 11-03, 10 BI-V150-specific operators were merged in six minutes (special polynomials, upsampling and padding backward, quantized max pooling, matmul smm, not_equal, pooling index backward); on the NVIDIA side, 12 PRs continued filling in sparse tensors, the cudnn family, views and shapes, and quantization and autograd internal operators. On 11-04 Iluvatar merged another 12, and #8396 reverted two prior updates that did not hold on BI-V150.
Enflame: All 5 merges on 11-04 were device-guard fixes (CUDA-only guard, im2col hardcoding, kl_div and arctanh, integer index clamping in upsample_nearest3d_backward, explicit failure on –override mismatch). The 41 GCU300 coverage tickets newly opened on 11-05 began landing in bulk the same day, with 25 cleared in one pass — approaches included narrowing 64-bit lane offsets to 32-bit, moving launch geometry to host-side precomputation, replacing _nv* external symbols with local implementations, and converting pointwise dynamic fallbacks into dedicated kernels.
Hygon and MetaX: #7388 on 11-04 added FP32 flash attention forward for Hygon; #7318 added channel-wise bmm_w8a8 INT8 fused scaling for MetaX; 11-04 also saw 9 Hygon FP32-specific open tickets (rsqrt, floor, nonzero, full-dimension reduction, masked_fill, nan_to_num, neg, masked_select, aminmax), all restricted to contiguous FP32.
Ascend and Moore Threads: #8110 on 11-05 added channel-wise INT8 BMM (+519/−3 lines); #7581 fixed UB overflow in Flash Attention forward and backward, and added varlen forward and dense D=256; Moore Threads #7246 rewrote mm on MP31 (single file, +2472/−146 lines), and #6706 added shape-aware TLE/SQMMA implementations for bmm and bmm.out (9 files, +2369 lines).
Backend key versioning: #8446 touched 12 files, +39/−38 lines, replacing seven bare vendor names with version keys. Its value is not naming consistency but that a wrong version fails instead of being silently skipped — under the old scheme, uv pip install ".[tsingmicro]" matched no extra, neither torch nor flagtree was installed, and setup.sh’s FlagTree check threw ModuleNotFoundError outright.
Tsingmicro and SiliconFlow: #8287 on 11-05 updated the tsingmicro backend to 1103 — 190 files, +23195/−914 lines, the largest single backend sync of the week; #6501 on 11-03 added three embedding bag operators in one go (supporting SUM/MEAN/MAX, weighting, padding exclusion, empty bags, and terminal offsets), +7494/−222 lines across 24 files.

FlagTree: Enhancements Become Runtime Switches, Hygon Gets TLE-Raw Working

Runtime switches: #1565 merged on 11-04, +123/−27 lines across 15 files, standardizing each FlagTree enhancement into a four-part pattern — a compile-time macro, a runtime knob (FLAGTREE_<NAME>, on by default, added to CACHE_INVALIDATING_ENV_VARS), a guard block consistent with surrounding code, and #else/#endif annotated with the macro name. Previously, once a compiler enhancement reached production, regressions could only be contained by rolling back the entire release; with switches pushed down, just that one enhancement can be turned off.
Stacked tickets: Between 13:02 and 13:15 on 11-04, 38 tickets were opened in fourteen minutes: 12 [TLE][NVIDIA], 4 [TLE][AMD], 7 [TLE][Iluvatar], 5 [FlagCX], and 5 [Iluvatar][Native]; #1563 also documented the dependency graph and validation gates for feature PRs, specifying which must merge in order and which can be validated independently.
Hygon TLE-Raw: #1508 on 11-05 added the tle.raw path for HCU — 53 files, +5106/−17 lines; it supports both eager and deferred modes, both HIP and MLIR sources (compiled to LLVM IR and embedded in Triton IR), and integrates DUSHMEM streaming collective communication, with three tutorials on ring shift, allgather GEMM, and GEMM allreduce. In the examples, sort’s HIP path is 1.29× faster than torch.
Correctness and observability: #1460 on 11-02 fixed TritonGPU pipelined cp.async degradation and WGMMA operand buffer reuse (a class of bugs that compute wrong results rather than erroring), and #1451 aligned WGMMA warp selection with upstream MMAv3; #1530 on 11-05 parses register, spill, stack, and shared-memory usage from ptxas diagnostics and writes them into TLE compiler metadata, with the repo side reporting 154 TLE MLIR tests and 11 new C++ unit tests all passing.
Other: #1236 on 11-02 added the XuanTie ZW810E cost model 1.1.0; #1524 on 11-04 added trigonometric compatibility and independent-rounding multiply APIs for AMD native, and #1370 changed DEB/RPM packaging to verify-only; #1572 on 11-05 made Moore Threads preserve explicit blocked layouts during dot conversion, and #1576 enhanced SoC-level dispatch for Enflame TLE.

FlagQuantum: Three Acceptance Lines Reach UP-04/05/06, Fault-Tolerant Compilation Integration Ticket Takes Shape

Scale: Merges across the five windows were 35, 21, 28, 29, and 5, totaling 118; the repo’s share of submissions fell from 58% in the three-day window to 43–47%, with the non-quantum side back above half.
910C and CI: #958 and #970 on 11-02 promoted Ascend 910C to a native provider and built a fail-closed regression lane, with dependency boundaries spelled out: Torch-FL taken from commit 3aebd0c on the feat/ascend-complex-lowering branch, and FlagCX from commit 6fe3631 of v0.14.1 plus a patch — binding reproducibility to source commits rather than binary packages.
Synthesis line: The 21 merges on 11-02 spanned three lines — UP (semantics), AO (arithmetic), and PF (performance): UP-01 lets functions decorated with @synth.qfunc directly write allocations, gates, and outputs; AO-00/01/02 successively establish an arithmetic baseline and independent oracle, protected common subexpression elimination and bit-fact normalization, and protected squaring plus constants and terminal XOR; PF-00/01 establish compile-latency and OS RSS baselines and reuse validated plan fields.
Frontend and algorithms: UP-04 on 11-04 added bounded uniform state preparation, scalar coherent control, bounded predicates, and checked phase helpers; UP-05 normalized frontend entry dispatch and extracted arithmetic lowering into a shared path; UP-06 supports U gates and array Hadamard for both Qmod and native qfunc. On the algorithm side, it added gate-level lowering for sparse chemistry SELECT, executable THC SELECT, and THC rotations lowered via QROM and phase gradients.
Detector error models: #1052 through #1069 on 11-04 successively added mutually exclusive fault parity, duplicate fault merging, multi-chunk round trips, sparse chunk projection, and per-round decoding, alongside the FTQC W1-B reference coverage map in #1072 — this line fills in the data path for quantum error-correction decoding, not algorithm demos.
Fault-tolerant compilation and CI: About 20 commits on the feat/ftqc-native-integration branch on 11-05 ported QVR’s phase gradients, scaled addition, measurement adjoints, and Hamming-weight phases section by section; the main integration ticket #1084 is open as a draft — 276 files, +31011/−92 lines. All 27 commits that day centered on CI quality gates — decoupling capacity from the hosted queue, restricting image eligibility, having required merge gates reject cancelled dependencies, bounded retries for artifact uploads, and migrating the core suite to a qualified offline environment.

FlagCX: Hygon bitcode Unified Packaging, Ascend 910C CI and traits Abstraction

Hygon: #667 on 11-02 was a structural change to the UIL line, adding the Hygon bitcode build and unifying how Device IR is packaged. Previously each backend packaged its own IR, and Hygon onboarding required maintaining a separate set of artifacts; after unification, the packaging cost for new backends drops.
Testing and semantics: #687 on 11-02 enforced SymMem coverage by adapter type in CI, preventing a pipeline from staying green when an adapter never ran symmetric-memory tests; #688 and #689 made the DU stream guard select by torch generation and back-ported the same fix to 0.14.0-rc2.
Ascend CI: #669 on 11-04 added the Ascend 910C pipeline and unified unit-test orchestration (+1559/−664 lines, 41 files), running Torch Python coverage on four platforms and removing duplicate CUDA performance tests; #686, raised from the FlagQuantum side, handles Ascend device completion tracking and tensor keep-alive.
Abstraction layer: #693 on 11-05 added CoopOps and Clock traits with an NVIDIA implementation, abstracting device capability queries into traits; #691 made Window resource teardown retryable; #694 added shared Net provider dispatch to DefaultBackend.

Torch-FL: Expansion at Both Ends (Apple MPS and Cambricon MLU), BPU Fixed to Usable

Scale: Merges across the five windows were 13, 5, 2, 29, and 12. All 29 merges on 11-04 came from the same author, yet pointed in two directions.
Apple Silicon: One end brought the MPS backend to “trainable” — adding addmm (the operator nn.Linear with bias actually lands on), convolution backward, comparison and reduction families, trigonometric and exponential families, cumprod, and tril, with convolution backward bit-identical to the reference implementation.
NVIDIA default path: #700 on 11-02 fixed the default NVIDIA conf routing 1485 operators to boxing kernels — the highest-impact fix of the week; #684 changed FP4’s half-byte shift to tensor operations to hit the already-routed overload; #687 narrowed the day-0 FlagGems override to the operators its own description defends.
Horizon BPU: #721 on 11-04 established that the eager path was in fact running every operator on CPU — the operator bucket ladder never exceeded 512 lanes, dual-input artifacts were submitted with a single-tensor descriptor causing silent wrong values, and hbdk4 could not import numpy under box64. After the fix, Run is exposed through the C ABI so the eager path bypasses the aten dispatcher; on RDK S600, relu at 262144 lanes dropped from 0.176 ms to 0.073 ms, and one conv block from 23.2 ms to 11.1 ms. #726 added DeviceChain, letting multiple BPU artifacts execute back-to-back on device without intermediate activations returning to the host: serialized elementwise dropped from 0.417 ms to 0.104 ms, and four independent dispatches from 1.667 ms to 0.673 ms.
Iluvatar and Kunlunxin: #698 on 11-02 pinned Iluvatar CI’s FlagTree to 0.7.0 (the version actually running on that chip), and #697 routed baddbmm through the vendor GEMM; #745 on 11-05 lifted Iluvatar’s operator cap so mul.Tensor can land on FlagGems; #756 on 11-05 kept Kunlunxin’s 3.2 GB FlagTree wheel out of the pip cache.
Capability queries: #708 on 11-05 added two query interfaces for fused-operator availability and device capability, so upper-layer code no longer uses tensor.is_cuda to decide whether a device can run fused operators — on flagos tensors that field is always False, which would silently push code like flex attention back to the eager path.

Training and Operator Libraries: Biren SUPA Enters the Stack for the First Time, DSv4 Sync Advances by Subsystem

Biren: TransformerEngine-FL #143 on 11-04 added the Biren SUPA vendor backend — +3608 lines across 7 files, the first time Biren appears as an independent backend in FlagOS training components. The PR body says only “Add BIREN SUPA vendor” with no hardware validation record attached — a skeleton-first effort.
FlagTensor and Megatron: FlagTensor #14 on 11-04 registered the MThreads/MUSA backend and added dedicated rewrites for seven transcendental functions — ACOS, ACOSH, ASIN, ASINH, ATAN, ATANH, and TAN — bypassing the libdevice path unsupported by MUSA Triton JIT (+300/−5 lines, 14 files), with the version aligned to 0.3.0. On the Megatron side, “DeepSeek-V4 upstream sync” advances by subsystem: #202 is the first, preserving precision-sensitive parameters and handling partial projections of the compressor and indexer (+3356/−775 lines, 26 files); #214 is the second, themed on mHC and expert-parallel overlap.
FlagTrain: Eight PRs on 11-02 concentrated on KMCompiler’s NVIDIA line (weighted_squared_relu, fused_h_aggregate forward and backward, bias_swiglu, scaled_masked_softmax forward and backward, fused_proj_rms_compute_h); #56 on 11-05 added fused h_post bda forward and backward, measured at 1.190× and 1.702× on nvidia, 6.714× and 3.568× on PPU, 6.057× and 2.590× on MC550, and 7.087× and 3.500× on Iluvatar; #57 wired scaled_masked_softmax to Ascend, MetaX, Moore Threads, and Iluvatar simultaneously.
FlagBLAS and FlagSparse: FlagBLAS #157 on 11-02 added an L1 BLAS backend and muBLAS reference for MUSA, covering fifteen operator groups from AMAX to SWAP; #159 on 11-05 optimized Ascend cgemm and scored it against an archived H100 baseline (under review). FlagSparse #115 on 11-03 merged in from the external NCIC-AlphaSparse repo (MUSA q4 wrap-up), and #117 on 11-05 merged another 62 files, +4809/−280 lines.
Inference side: FlagGems-sglang #279 on 11-04 merged 6 model-level operators together with per-platform vendor overrides — +13061/−79 lines across 85 files; rms_norm is mathematically and ABI-identical to the existing one_pass_rms_norm, so it was merged as _mthreads, _thead, and _hygon overrides rather than as a new operator; #294 on 11-05 unified explicit device selection under GEMS_VENDOR, keeping DNN_VENDOR but emitting a FutureWarning. FlagGems-vllm #1048 on 11-05 implemented fused_indexer_weight_scale on Ascend with TLE — two-stage pipelining, 4096-element tiling, with shapes taken from real GLM-5.3-Flash calls.
Vision: FlagCV, only founded on 10-14, saw 8 commits and 4 merges this week: #5 added an independent OpenCV CUDA add reference adapter, #6 aligned add’s evaluation with FlagGems-sglang’s pytest contract, and #7 unified device selection under GEMS_VENDOR.

Supporting Infrastructure: Packaging Moves to verify-only, Testing and CI Shift Forward into the Review Chain

Packaging: 15 merges on 11-04 spanned seven repos (FlagBLAS, FlagSparse, FlagTree, FlagFFT, FlagDNN, FlagTensor, libtriton_jit, flagtree-cpu), with the core action being to unify DEB/RPM workflows into verify-only — validating only that builds succeed, without republishing artifacts. Supporting fixes addressed file conflicts between FlagFFT and libtriton_jit, the nlohmann_json dependency in RPM containers, and FlagDNN configuring NVIDIA builds when no importable torch is present.
optest: Five PRs on 11-02 centered on test infrastructure (managing FlagTrain vendor dependencies with uv, fast-failing on insufficient shared memory, package index retries, S60 shared memory, and isolating concurrency by library and backend); seven on 11-03 added Feishu test summaries and configurable timeouts; #38 on 11-04 probes FlagGems operator inventories by vendor (which operators each backend actually registers, no more guessing), #35 added NVIDIA baseline scripts, and #36 fixed “collecting test markers but actually executing the tests.”
CI and docs: FlagTree #1457 and #1513 write FlagGems CI results into Feishu Bitable, and #1568 names the responsible person in Feishu when CI fails; docs #575 was opened by a bot to sync the ModelScope model inventory; OpenCourse #5 through #7 updated all lab materials to mainline; FlagQAI #30 tightened the macOS sandbox (local Python jobs, headless sessions, native shell, search targets, and subprocesses each brought within bounds).

IV. Member Units and Vendor Adaptation

Hygon: The Full DTK 26.10 Delivery Chain and Two FP32 Lines

Images and dependencies: Hygon was the most concentrated effort this week, with 21 build-infra merges covering both the base and runtime layers of 2.3.0, plus the flagcx wheel released with the +dtk2610 suffix, removal of the invalid HIP_VISIBLE_DEVICES, and addition of amdsmi. The cost of DTK 26.10 lies almost entirely in dependency resolution and packaging, not in the kernel itself.
Communication and training: FlagCX #667’s unified packaging of Hygon bitcode and Device IR marks the first time Hygon has obtained a build artifact form consistent with other backends on the communication library side; FlagScale #1299 is under review, adding Hygon DCU hardware health sampling, while #1255 through #1257 add three diagnostic categories—missing CPU-side entry in NCCL, collective communication and P2P mismatch, and internal hangs—pointing at “whether problems can be localized when ten-thousand-card training fails.”
FP32 forward: #7388 adds an explicit FP32 path to the Hygon implementation of _flash_attention_forward while preserving ATen’s five-output schema and existing FP16/BF16 behavior. The supported scope is written very narrowly: fixed length, contiguous 4D BSHD, square MHA with Q/K/V of the same shape, head dim of 64 or 128, dropout of 0, no window/alibi/seqused/varlen, with unsupported combinations raising errors directly. The implementation uses IEEE FP32 dot products for QK and PV, initializes the online softmax maximum with -inf, and uses exp2/log2 for long sequences.
Compiler and training performance: FlagTree #1508 enables TLE-Raw support for HCU; build-infra #1654 lays out two LLVM trees simultaneously for flagtree’s HCU build, indicating that the LLVM version has not yet converged to a single tree; TransformerEngine-FL #153 adds an optional BF16 expert GEMM path for Qwen3.5-35B (opt-in, without changing default behavior); FlagAttention #117 and #123 add GLA optimization and the AttnRes backend, respectively.

Ascend: Beyond the 910C Quantum Line, Runtime, Execution Mode, Operators, and CI Advance on Four Fronts

Quantum and communication: The 910C native provider and ARM64 regression lane are the largest single item this week (see Top Stories); the accompanying FlagCX #686 handles Ascend device completion tracking and tensor keep-alive, a prerequisite for the quantum stack at the communication layer.
Runtime: The CANN 9.2.1 base layer covers only 910B; the python 3.12 and torch 2.13 constraints stem from the requirement that the wheel match the version of the python tree bundled with CANN; this layer deliberately leaves FlagTree and FlagCX empty, and will be re-pushed after adding OCI provenance labels on 11-04.
Execution mode: vLLM 0.28’s FULL_DECODE_ONLY native graph covers Qwen3.6-27B and Qwen3.6-35B-A3B, with decoding going through torch.npu.NPUGraph while prefill, vision encoding, and sampling remain outside the graph.
Operators and CI: FlagGems #8110 adds channel-wise INT8 BMM (+519 lines, -3 lines); #6060 adds an Ascend backend for mm_w8a8_int8 and mm_w8a8_int8_out (supporting pre-quantized INT8, FP32 scalar or per-row/per-column scale, optional bias, with BF16/FP16/FP32 output, and no asymmetric zero points); #7581 fixes Flash Attention UB overflow and adds varlen forward and D=256; FlagCX #669 builds the 910C CI pipeline; FlagTree #1413 fixes XCS’s lightning-indexer UB overflow and swiglu precision.

DAMO XuanTie: Operator Batches, Cost Models, and PPU Attention on Three Lines

Operator layer: The 13 specialized operators on 11-02 were merged within 43 minutes, covering special functions, 3D convolution, quantized LSTM, matrix norms, and pooling backward; at an average of 3.3 minutes per merge, this shows that review can now digest batched operator tickets in parallel by backend.
Compiler layer: The ZW810E MM/MV cost model package 1.1.0 is incorporated into the FlagTune model catalog, containing 8 BF16 mm variants and 2 mul models—the first complete cost model for auto-tuning on XuanTie.
Inference and communication: FlagGems-vllm #1038 adds both the Tianshu and XuanTie backends for chunk_kda; sglang-plugin-FL #166 makes the RS+add+RMSNorm+AG fused ring kernel an option for pure TP prefill (under review), reusing the pccl 28-channel ring on PPU 810E; FlagAttention #127 opens a new Wall Attention for PPU-ZW810E; FlagGems #8446 sets the backend key to thead-ppu210.

Kunlunxin: Batch Performance Patches and a Shape Contract for a Silent Error

Cadence: Ten merges on a single day on 10-30, fourteen on 11-02, eleven on 11-03, and five new tickets on 11-04. The team advances in batches rather than following upstream’s cadence, favoring direct pointers and single-issue in the implementation, with separate block widths for bf16.
Correctness: #8038 fixes a silent error caused by the foreach fast path comparing only element counts rather than shapes—tensor lists with different shapes but the same element count all inherit the first tensor’s shape, and the output neither errors nor overflows. Such defects are more dangerous than being ten times slower: benchmarks won’t find them, and downstream models only hit them as precision anomalies.
Performance: #8255 accelerates argmin using the vendor min.o’s SIMD payload and segmented wide-row parallelism; #8028 brings four operators above the 0.8 Gems Speedup threshold (upsample_nearest2d 1.202, unique_consecutive 1.053, fake_quantize_per_tensor_affine 0.827, foreach_clamp_max_scalar 0.967); #8250 makes inner actually participate in compilation on XPU and retunes the tile; #8262 optimizes lcm with the extended Euclidean algorithm.
Fixes and inference stack: New tickets concentrate on the sum_dim fallback, the fake_quantize series, pipeline event overflow in lstm/gru, tt.gather degradation in linalg_matmul and linalg_lu_solve, and avg_pool1d aborting the process; sglang-plugin-FL #155 upgrades the Kunlunxin backend to SGLang 0.5.18 (under review), and the vLLM 0.28.0 wheel directory line is added by #1637.

MetaX: 0.28 Empty Adaptation, Debugger, and New Attention Structures

Inference plugin: C550’s 0.28 adaptation is self-sufficient via the plugin when upstream has no corresponding branch (#554); the installation form explicitly rejects site-packages startup hooks and clears out 15 legacy zz_fl_*.pth hooks; the 0.32 C550 adaptation #693 was opened the same day, running both lines in parallel.
Debugging and attention: FlagPrism #18 adds the MACA runtime adapter, build modules, Python bindings, and tests—the first time FlagPrism brings MetaX into the debugging chain; FlagAttention #119 and #122 add Parallax prefill/decode and BF16/INT8 Hy3 attention, respectively, representing multi-chip deployment of new model structures rather than tuning of existing operators.
Operators and industry side: FlagGems #7318 adds channel-wise bmm_w8a8, and #8414 adds layernorm (under review); Torch-FL #702 corrects the skip reason for SDPA test cases (previously attributed to fp32, when the actual cause was something else), a test-credibility fix. On the industry side, the Q3 report discloses the MXMACA 3.9.0 release and that build support code has been merged into LMCache, while the model side claims Day 0 adaptation for GLM, Qwen, and Hunyuan.

Moore Threads: Conv1D Pulls All 26 Benchmark Cases Above the 0.8× Line

Complete case: #6754 adds conv1d backend coverage for MTT S5000, raising the official conv1d_padding benchmark from 18/26 cases meeting the bar to 26/26 cases at no less than 0.80× torch; previously all FP32 K3/K5 padding cases were only at 0.41× to 0.53×. Three layers of changes landed together: routing changes to remove redundant padding and bias allocation, a new dedicated Triton-MUSA Conv1D kernel that splits a 3D grid by M=N×Lout, and weight pre-packing paired with SQMMA with precision compensation.
Inference and operators: MUSA 0.28 brings in native MCCL, FX/eager compilation, and segmented native graphs in one go, with a runtime baseline of four S5000 cards, BF16, TP=4, TorchMUSA 2.9.0, and MUSA SDK 4.3.5; on the compilation side, RMSNorm, SiLU, and rotary go through explicit MUSA operator boundaries, and the reference RMSNorm preserves the target-side FP32 accumulation contract.
Training components: FlagTensor #14 registers the MUSA backend and adds dedicated rewrites for seven transcendental functions; FlagBLAS #157 adds MUSA’s L1 BLAS; FlagAttention #121 adds Moba attention and fixes imports; FlagGems #8097 optimizes skinny FP8 matrix multiplication (transposed dot product plus GEMV tile).

Enflame: 41 New Tickets, 25 Cleared, Rewriting Rather Than Translating

Scale: Of the 66 new FlagGems tickets on 11-04, 41 are for GCU300; 25 were merged at once on 11-05, all prefixed with KernelGen and Enflame.
Four categories of changes: First, splitting out external symbols, replacing _nv_nearbyintf, __nv_y0f/y1f, __nv_j0f, normcdfinv, and others one by one with local implementations; second, switching algorithm paths—special_chebyshev_polynomial_t to a dedicated kernel, linalg_householder_product to a single-pass reflection sweep, linalg_inv_ex to a single-kernel Gauss-Jordan, and compute_linear_combination replacing the outer product with tl.dot; third, removing incompatible compile-time features—renorm’s auto-tuning causes this backend’s compiler to abort outright, so the whole block is dropped, and fake_quantize switches to magic-add rounding; fourth, fixing launch geometry, correcting the launch geometry of special_i1e and special_bessel_k0 item by item.
Device guards: Another 5 tickets on 11-04 are all CUDA-only guard fixes, including the im2col hardcoded guard, kl_div and arctanh, integer index clamping in upsample_nearest3d_backward, and explicit failure when –override does not match the operator name.
Other: vLLM 0.32’s S60 adaptation #675 is under review; FlagTree #1494 temporarily disables the 03-topk test to stop the bleeding; FlagTree also removes the enflame3.5-guc400 CI/CD workflow during the same period, which is a CI roster change following hardware generation turnover and should not be read as termination of the product line; FlagAttention #118 adds the parallax operator.

Iluvatar: Ten Merges in Ten Minutes on BI-V150 and the Compiler’s Native Route

Operator production line: Ten merges in six minutes from 16:04 to 16:10 on 11-03, and another 12 on 11-04 (two of which were rollbacks of prior updates that do not hold on BI-V150). Coverage includes triangular margin loss, pseudo-inverse, matrix multiply-add, tensor inverse, index reduction, inverse gamma, 3D grid sampling, 3D transposed convolution and its backward, linear combination, and CTC loss.
Compiler side: All 12 new FlagTree tickets are [Iluvatar][Native] and [TLE][Iluvatar]—thread count derived from the target warp size, vector access width selected by element size, explicit load-vectorization compile options, explicit layout across control flow, SME transport, and physical grid barrier domains. The direction is to replace “generic Triton assumptions” with “generation according to target machine specifications.”
Inference and training: sglang-plugin-FL #139 adds SGLang 0.5.18 empty adaptation; Torch-FL #745 lifts the operator cap, and #753 and #762 use ixblas axpy to cover the add family (under review); FlagScale #1322 and Megatron-LM-FL #213 add the Iluvatar pipeline.

Tsingmicro: An Engineering Trade-off Where TXDA Does Only Eager

Trade-off: #642’s segmented native graph has been implemented and passes the full gate for two models under TP8 (snapshots R10 and R6d), but Dense TP1 correctness was never resolved. Rather than choosing “a graph mode usable only at some parallelisms,” the author deletes the graph capture and splitting implementation, rejects graph and compile configurations at the configuration stage, and points users directly to –enforce-eager. MLA, sparse attention, speculative decoding, and context parallelism are each rejected item by item along their specific unsupported paths.
Validation environment: 8× TX8110 64G, with vLLM in the image being 0.28.0+empty—built from upstream tag commit 2cf0a69 with the target device empty, without the vllm._C extension, with all kernels coming from the plugin or FlagGems. This effectively turns “whether the plugin is truly self-sufficient” into a hard constraint.
Other actions this week: FlagGems #8287 updates the tsingmicro backend to 1103 (190 files, +23195 lines, -914 lines); Torch-FL #704 brings tsingmicro into the conf and registration-set consistency check, from which the platform had previously been excluded among six platforms; the backend key is set to tsingmicro-tsm260610.

Cambricon: From “It Runs” to “Zero Fallback”

Integration form: MLU enters Torch-FL as a vendor-native platform, adding the libcnrt runtime layer and a torch.mlu shim, running on stock torch 2.10.0+cpu, with end-to-end testing on eight MLU590-M9 cards; the CI lane was withdrawn the same day, writing “integrate the backend first, add CI later” in the commit message rather than leaving a permanently red pipeline.
Fused attention: SDPA was previously decomposed into three leaf operators on Cambricon because cambricon was excluded from composite coverage, so every attention had to write the B×H×S×S score matrix to HBM and read it back. At batch 2, 4 heads, and sequence 4096, that matrix is about 256 MB; #748 and #749 bring CNNL fused forward and backward back into coverage and wrap them as a C++ autograd Function.
Fallback elimination: 188 of the 190 fallbacks came from aten::mul.out, showing that this kind of cleanup relies on a census rather than guesswork; after the two changes execute via CNNL on MLU, the full Qwen3 training step reports zero operator CPU fallback. Both Cambricon neuware 4.4.3 and 4.7.2 image layers are within 2.3.0 coverage.

Horizon Robotics and Biren: One Fills in the Basic Operator Family, the Other Stops at the Skeleton

Horizon Robotics: Three merges on 11-02 move conv, batch norm, and pooling from the eager path to the BPU, and carry avg_pool with an equivalent depthwise convolution; after fixing three hard faults on 11-04, relu and conv block latency drop to 0.073 ms and 11.1 ms respectively, and DeviceChain compresses four dispatches from 1.667 ms to 0.673 ms. There were no new commits on 11-05, a quiet period following the previous round.
Biren: TransformerEngine-FL #143 enters the training components with the SUPA backend, adding 3608 lines across 7 files, but without attached hardware validation records. There are two paths for a new chip to enter FlagOS—starting from training components or from the operator production line; Biren takes the first and stops at the skeleton, with validation depth not on the same level as Tsingmicro or MetaX.

V. Ecosystem and Community

FlagOS 2.2’s industry cases deliver quantifiable returns for the first time

China Telecom: Xingchen Xing4.0-29B-A4B (29B total parameters, 4B activated) was trained end-to-end on an Ascend 910C cluster, with precision alignment and deployment validation across 10 domestic chips completed on the day of release. The crux was the multi-channel residual operator mHC: the official N-card implementation itself runs about 10% slower, the first Ascend version dropped 50%, and the team’s in-house version long stalled at 25%; after registering FlagGems’ specialized optimized operator into the MindSpore + CANN + Ascend NPU training pipeline, cluster slowdown was cut from 25% to 12%, and this adaptation has been open-sourced and merged into MindFormers.
Knock-on effects: Agent scenarios average 70K prompt tokens with a maximum of 200K; after rewriting 12 long-sequence operators on FlagOS, first-token latency fell 19.87% and decode speed rose by more than 20%; the hotline voice pre-processing pipeline aggregated and rewrote Spectrum-class operators, achieving a 10x speedup on three chips from Huawei, Moore Threads, and Iluvatar.
iSoftStone: Its Tianyuan intelligent computing platform bills by token, and GLM-5.2 generates a single token in 17.79 ms on four Ascend 910C servers, while the model provider’s published API admission threshold is 16.13 ms; after adopting FlagOS, it enabled PD disaggregation (Prefill and Decode each on two servers) with optimization on both sides, bringing latency within the admission threshold.
A set of totals for 2.2: Nine operator libraries totaling 1,454 operators; FlagTree alone covers 20 vendors’ chip backends; overall performance up 27.6% across 10 chips and over a thousand operators; Day0 adaptation of new models to 12 chips; 107 community members; 460,000 quarterly downloads, 4.76x the previous quarter. The article’s conclusion: “Judging the maturity of domestic AI infrastructure is not about how many chips are supported, but whether a newly released model can run with deliverable throughput on launch day by changing only configuration.”

The edge-side narrative: ARM CPUs and 35 chips

Measurement basis: Without GPUs or NPUs, pure ARM CPUs run MiniCPM and Qwen at hundreds of tokens/s, with measured gains of 21%–25% based on SME2 and I8MM; FlagOS multi-chip adaptation follows “optimize once, reuse across devices,” covering 21 chip vendors and 35 chips.
Scope difference: The 21 vendors and 35 chips here are edge-side and device-side adaptation statistics, not the same dimension as the 107 community members and 12 Day0 chips announced at the 2.2 conference, and should not be conflated when cited. Treating the edge side separately means the narrative expands from “multi-chip on the cloud side for training and inference” to “multi-chip on the device side,” consistent with Torch-FL’s direction of adding the Apple Silicon MPS path.

Wuzhen Summit and member organization updates

Summit: The 2026 World Internet Conference Wuzhen Summit was held from 11-02 to 11-05 under the theme “Open Source and Openness, Co-building and Sharing,” with 27 sub-forums; the accompanying “Open Source Thematic Ecosystem Experience Pavilion” opened at the Wuzhen World Internet Science and Technology Museum on 11-01, showcasing major AI open-source achievements in a concentrated exhibition for the first time. Public reports within the window did not mention FlagOS or its components; this item is recorded only as external context, with no attribution.
Member organizations: MetaX and Moore Threads both received the “Outstanding Contribution Award” at the summit; reports of Enflame Technology’s listing on the A-share STAR Market appeared on 11-03, but a review on 11-06 confirmed its actual listing date was September 11 (688801), making it a retrospective piece rather than a new event within the window, and thus not counted as a new fact this week. The three companies’ FlagOS-side activities differ — MetaX and Moore Threads merged 0.28 adaptations that day, while Enflame had four correctness fixes in FlagGems GCU300; progress at the capital and recognition level has not changed the pace of technical investment.
Parallel ecosystem: The “Intelligent Computing System Innovation and Open Ecosystem” sub-forum at the GAI+C conference held on 10-31 released three joint achievements — “Jiuyuan × Phytium,” “Jiuyuan × TileLang,” and “Jiuyuan × SenseTime Multimodal Large Model Training and Inference Suite” — and launched the 2026 Autumn Qiyuan AI Competition. In his keynote, Chinese Academy of Engineering academician Zheng Weimin pointed directly at domestic compute’s problems of “cards that are hard to use, chimney-style adaptation,” advocating a unified software stack to support “one codebase, no modifications” cross-platform operation — structurally similar to FlagOS’s technical proposition, but a different ecosystem line. On 11-04, the BAAI community published the “World’s First Frontier Open-Weight AI Risk Management Framework,” an outward contribution at the open-weight model governance level that complements FlagOS’s open-source stack narrative.

Channel check: component-level news remains at zero hits; narrative still depends on official channels

Google News: 24 sets of Chinese and English query terms were checked daily; FlagOS, FlagGems, FlagScale, FlagTree, FlagPerf, FlagCX, KernelGen, flagos-ai, and BAAI-related English combinations had zero component-level hits all week; hits clustered around member organizations and industry terms, with content consisting of quarterly reports, stock prices, financing, events, and popular-science pieces, all removed in bulk per the rules.
CSDN column: Only two new articles appeared all week, both on 11-05 (11:23 and 14:10); the remaining entries are old articles from August to October, with the latest stopping at the 10-29 MiniCPM-OCR and Jev Day0 adaptation; the three articles ranked at the top of the page — GLM-5.3-Flash, Qwen3.8-Flash-Next, and LightX2V — are old pieces from 8-28, 8-27, and 8-27 respectively.
HN and BAAI community: Eight HN Algolia queries yielded zero direct hits all week, only broad matches for FlagOS and BAAI; the BAAI community search page is client-rendered, so scraping could only confirm no FlagOS entries on the homepage, and this channel continues to be recorded as “no new visible entries.”
Assessment: GitHub saw pushes to 21 to 26 repos and 94 to 177 merges in a week, contrasting with zero component-level hits on the news side. FlagOS’s external narrative still relies heavily on the CSDN column, the BAAI community, and conferences, and third-party media coverage of component-level progress has yet to take shape.

VI. Trend Observations

Images first is a planned cadence; 11-13 is the hard boundary: All 23 base and 23 runtime images are tagged 2.3.0, while the manifest file will only be generated at the 11-30 feature freeze; per the schedule, the FEP merge deadline is 11-13, rc0 is 11-30, rc1 is 12-07, rc2 is 12-14, code freeze is 12-25, and GA is 12-30. Images running ahead of the manifest is not a disconnect; what is really worth watching is whether the seven new FEPs can be merged before 11-13, and whether the cuda13.3 line will move the torch version again.
Multi-chip adaptation has shifted from “template copying” to “per-backend accounting”: For the same vLLM 0.28.0, the four backends yield four strategies — SpacemiT proactively gives up graph mode in exchange for a correctness boundary, MetaX makes the plugin self-sufficient when there is no upstream branch, Moore Threads folds graphs into a single file and brings in native MCCL, and Ascend only does decode graphs. Adaptation work no longer has a unified template; each vendor trades off according to its own validation capability and downstream model requirements, and the hidden cost is maintaining both 0.28 and 0.32 environments simultaneously.
Benchmark comparability is becoming new infrastructure: FlagGems converges the H800 reference readings of four operator categories into a unified JSON with 23 entries in two minutes, optest probes the operator lists actually registered by each vendor and fills in NVIDIA baselines, and FlagTree and FlagCX push results to Feishu multi-dimensional tables and extend coverage to four platforms. This line does not produce operator counts, yet it determines whether cross-backend scores are trustworthy; this week 26 entries fell on the CI and benchmarking side, accounting for 14.7% of single-day merges.
The bottleneck sits stably at the review end, not the production end: The 11-04 daily report records 1,602 open items under review across the organization, a merge-to-in-review ratio of about 1 to 9; within the 11-05 to 11-06 window there were still 288 and 255 updated in-review items, with the FlagGems and FlagTree repos accounting for 60%. During the same period, several PR bodies carry AI agent tool, model, and human review fields, indicating that the coding end has already been amplified by agents and the capacity bottleneck has shifted to review and validation environments.
Both paths for onboarding new chips have been proven; the gap lies in validation depth: Biren enters TransformerEngine-FL via the SUPA backend, a skeleton-first approach with no hardware validation record; Cambricon enters Torch-FL via its native platform and tests on eight MLU590-M9 cards, reverting the training step to zero the next day; SpacemiT runs a dedicated operator line at ten operators a day. Onboarding speed is no longer the threshold; whether hardware gate records can be produced is the dividing line.
The engineering path for the quantum stack is now clear: The 167 hardware acceptance items on 910C, the resource accounting for x*256 dropping from 28 allocated qubits and a 4 GiB state buffer to 19 and 8 MiB, and the fail-closed regression lane together constitute three verifiable pieces of evidence — “semantics, resources, hardware.” None of this week’s 27 commits concerns the quantum algorithm itself; all are for making tests trustworthy and the runner reproducible, indicating a consensus that paying the infrastructure bill first is the right move at this stage.
The operational shortfall remains external narrative: The 2.2 industry cases can already cite hard numbers such as 25% to 12%, 19.87%, and 10x, yet component-level news has had zero hits for several consecutive windows, and third-party media coverage has yet to take shape. For FlagOS, the gap between technical output and external visibility may affect ecosystem expansion speed more than any single backend’s feature gap.

Appendix: Materials and Verification

Materials List

Date	Daily Report	Research Window	Nature
11-02 (Mon)	FlagOS Community Daily	10-30 06:00 ~ 11-02 06:00, 72 hours	Covers the 10-31 and 11-01 weekend, continuing from the previous issue’s cutoff
11-03 (Tue)	FlagOS Community Daily	11-02 06:00 ~ 11-03 06:00, 24 hours	Back-to-back
11-04 (Wed)	FlagOS Community Daily	11-03 06:00 ~ 11-04 06:00, 24 hours	Back-to-back
11-05 (Thu)	FlagOS Community Daily	11-04 06:00 ~ 11-05 06:00, 24 hours	Back-to-back
11-06 (Fri)	FlagOS Community Daily	11-05 06:00 ~ 11-06 06:00, 24 hours	Final issue of the period

Verification Notes

GitHub side: All five daily reports performed full push verification across the 61 repositories of the flagos-ai org, cross-validated with three independent queries: commit search, merged PR search, and in-review PR search; Releases and Tags were re-checked daily against the Release atomic source for 31 repos and the Tag atomic source for 8 repos, with zero additions for the entire week. Branch attribution and default-branch commits were separately re-verified atomically to avoid misrecording PR branches or gh-pages deployments as default-branch activity.
Versions and dates: The layer names, version numbers, and dates for 2.3.0 are taken from the PR bodies and changelog records in build-infra; the 2.3 schedule is taken from the release timetable in the community repo; the adaptation status of vLLM 0.28.0 and 0.32 is based on the merge and in-review status of the corresponding PRs, and in-review items were not written up as merged.
Vendor actions: Entries for member organizations are based on actual commits and PRs in the respective flagos-ai repositories; industry-side figures are taken from public reports with the nature of the source noted; earnings, awards, and IPO-related content are explicitly marked as company-side developments and not counted as project progress. The date of Enflame’s IPO was corrected to September 11 upon re-verification in the 11-06 issue, and this report adopts the corrected figure.
Scope note: The 11-02 issue covers a 72-hour window and cannot be directly added to or compared with the 24-hour windows of the other four issues; when giving totals, this report lists both the five-day cumulative figure and the figure for the four complete 24-hour windows. The 21 device-side vendors and 35 chips, and the 107 members and 12 Day0 chips of the 2.2 conference, belong to different statistical dimensions and were not mixed when cited.
Uncovered items: There were no missing daily reports during the period; the community repo’s release-2.3.yaml has not yet been created, so there is no release manifest to verify; the BAAI community search page is client-rendered, so only the homepage could be verified, and no count-level conclusions can be given.