Research window: Past 3 days (2026-09-18 05:18 ~ 2026-09-21 05:18, Beijing time; Monday window covers the weekend) Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), Shanghai Securities News / cnstock.com, Cailian Press / STAR Market Daily, Lieyunwang, 36Kr, GeekPark, Tide News, Gasgoo, LinuxGizmos, riscv.org, openRuyi official site, RISC-V International official site, RISC-V International member company website inspection (391 companies), and GitHub (XiangShan / GEM5 / NEMU / difftest / XSCache, DAMO XuanTie, Sophgo, SpacemiT, Sipeed, Radxa Linkr, openRuyi-Project and other organizations’ and key repositories’ push and commit searches)

Index

  • Today’s Highlight: EVAS Intelligence completes a new round of nearly RMB 2 billion in financing, post-money valuation approaching RMB 15 billion (09-18)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan NEMU/difftest: batch of fixes and adaptations for AME matrix extension (09-18 ~ 09-20)
    • XiangShan repository group: branch-level development active on store prefetch and CHI integration, no new merges to mainline (09-18 ~ 09-20)
    • openRuyi: ~20 SPECS package submissions, dense cloud-native and toolchain updates; September release not yet published (09-19 ~ 09-21)
    • openRuyi ceph-ci: Ceph RISC-V porting continues, precommit-hooks new repo lands (09-18)
  • II. Product and Ecosystem Developments
    • 2026 Semiconductor Ecosystem Development Conference: RISC-V international standard timeline and Lanxin LX500 commercial progress (09-20 report)
    • SEMICON India 2026 concludes: DIR-V competition winners announced, C-DAC releases AI and quantum platforms (09-20)
    • Openchip: two-year tape-out path for Europe’s sovereign RISC-V chip BER10 (09-17, first day of window)
    • Nordic releases nRF54LC10A: multi-protocol SoC with Cortex-M33 plus RISC-V coprocessor (09-17 ~ 09-18)
  • III. Deep Dive on Domestic Teams
    • DAMO XuanTie: zero_stage_boot releases XuanTie_V1.4.0 stable version (09-18)
    • SpacemiT: batch branch sync across nearly 30 repositories in the K3 product line; Zhejiang University of Technology’s first class of the semester visits SpacemiT (09-18)
    • Sophgo: ZSBL releases v3.2.0; sophon-tools ships 2.1.x twice with f2fs support (09-18 ~ 09-20)
    • Sipeed: SLogic logic analyzer software stack refactored, driver shared kernel and three-platform CI (09-18 ~ 09-20)
    • Radxa Linkr: v1.5.0 released, plugin center and network plugin launched (09-18)
    • Member website inspection: 391 companies completed, no substantive developments found (09-21 verification)
  • IV. Embodied Intelligence and Robotics Special Section
    • Suzhou Ruixin × Qiyuan Robotics: Highlight D35 dataflow physical AI chip enters humanoid robot ecosystem (09-20)
    • SpacemiT spacemit-robotics: ORB-SLAM3 runtime repository and usage guide land (09-20)
    • SpacemiT spacemit-robotics: ros2_humanoid adds ZMQ policy switching and voice control (09-18)
    • Sophgo sophon-demo: π0.5 VLA porting examples and CV84X6 batch adaptation (09-19)
  • V. Summary and Trend Observations

Today’s Highlight: EVAS Intelligence completes a new round of nearly RMB 2 billion in financing, post-money valuation approaching RMB 15 billion

Date: 2026-09-18　Sources: Lieyunwang via Tencent News “EVAS Intelligence Completes New Round of Nearly RMB 2 Billion in Financing, Post-Money Valuation Approaching RMB 15 Billion”, 36Kr English “Yixing Intelligence Secures 2 Billion Yuan New Financing”

RISC-V cloud AI compute chip company EVAS Intelligence was confirmed by multiple media outlets on 09-18 to have completed a new round of financing: nearly RMB 2 billion (approximately USD 295 million), with a post-money valuation approaching RMB 15 billion. The round had more than 20 investors, including Huatai Innovation, Zhongding Capital, SMIC Capital, Jiuan Medical, Tongfu Microelectronics, Saiyi Industrial Fund, Heli Capital, and Xinxin Leasing, among which Xinxin Leasing is a sub-fund of the National Integrated Circuit Industry Investment Fund Phase I (Big Fund Phase I). This is another large sum the company has secured within months, following its RMB 1.5 billion Series B in the first half of this year and a strategic investment from China Mobile, and is currently the largest single disclosed financing in China’s RISC-V sector.

Product and commercial-side information was released alongside: the first-generation Epoch cloud compute chip has achieved large-scale mass production delivery, with native support for block-wise quantized FP8; the industry’s first RISC-V AI compute supernode (64-node orthogonal backplane-free, E200-L liquid-cooled OAM modules, inter-chip hundred-nanosecond-level interconnect) announced during WAIC in July this year has completed cluster deployment at an operator data center in Shijiazhuang, Hebei, validating a ten-thousand-card deployment path; the next-generation cloud chip has completed tape-out, with the company citing an iteration cadence of “one generation per year.” On the ecosystem side, the company is advancing the open-sourcing of the VISA virtual instruction set, with its software stack natively compatible with PyTorch, TensorFlow, JAX, and ONNX, and collaborating with communities such as vLLM, Triton, and FlagOS.

The policy backdrop is worth noting for comparison: MIIT and the National Development and Reform Commission recently jointly issued the “15th Five-Year Plan for the Development of the Electronic Information Manufacturing Industry,” which in the hardware-software synergy section proposes to “advance the R&D and industrialization of the fifth-generation reduced instruction set (RISC-V), and support the application of RISC-V chips in fields such as artificial intelligence and embedded systems.” The valuation the capital market assigned in this round is directly related to the policy direction and the company’s positioning as “the first mass-production-grade RISC-V cloud compute” provider. A boundary worth retaining: a valuation approaching RMB 15 billion does not equal realized performance; the company is four years old and its first-generation chip has just entered volume delivery, so the pace of subsequent orders and revenue realization is the harder test.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan NEMU/difftest: A Batch of Fixes and Adaptations for AME Matrix Extension

Date: 2026-09-18 ~ 09-20　Source: NEMU PR #1224, NEMU PR #1217, difftest PR #962

NEMU merged 5 commits during the window. Two target AME (matrix extension): detecting reads of undefined tile register regions (#1224, 09-20), and restricting the comparison range of matrix loads to the active region (#1217, 09-18). Two target differential testing: marking CSR dirty bits for the SHARE REF scenario (#1220, 09-20), and switching to memmove for exporting GCC registers to improve export performance (#1219, 09-18). One targets virtualization: riscv64 retains the final RVH TLB refill path instead of forcing a fault (#1218, 09-18). On the difftest side, two companion commits: #962 adapts AME packed events to the NEMU ABI (09-18), and #971 disables elfloader debug prints (09-20).

This group of commits was pushed consecutively by the same developer, with the main thread being to make matrix extension behavior consistent across NEMU, difftest, and RTL—including clarifying boundary semantics such as “read behavior for undefined register regions.” The dense landing of AME-related support in the XiangShan verification chain indicates that matrix computation is one of the current focal points of its instruction set extension work.

1.2 XiangShan Repository Group: Branch-Level Development Active in Store Prefetch and CHI Integration, No New Merges on Mainline

Date: 2026-09-18 ~ 09-20 review　Source: XiangShan branch activity, GEM5 branch activity, XSCache branch activity

During the window, the master branches of the main XiangShan repo, GEM5, and XSCache saw no new merge commits, but branch-level pushes were dense. The main developments fall into four categories: first, the store prefetch optimization series is being advanced in parallel in XSCache and XiangShan (multiple variant branches such as size8 and size4-shadow-dedup, exploring memory access prefetch strategies); second, on the GEM5 side, a CHI integration rebase branch (feature/chi-dev-v2-rebase-xs-dev-20260920), a cacheline replacement split (split-store-perm), and an I-prefetch alignment branch were created, corresponding to coherent bus integration and instruction fetch optimization; third, the main XiangShan repo saw a TAGE branch conflict fix (fix-tage-bank-conflict), RAS testing (test-ras-1), fast interrupt (fast-interrupt), and Kunminghu V3 (kunminghu-v3) branch updates; fourth, some batch performance experiment branches (codex/perf-128-*). Active branches with mainline pending merge is a normal state during parallel development; this issue records milestones and will follow up after merges.

1.3 openRuyi: About 20 SPECS Package Commits, Dense Cloud-Native and Toolchain Updates; September Release Not Yet Out

Date: 2026-09-19 ~ 09-21　Source: openRuyi commit log, openRuyi official news page

The openRuyi rolling release repository landed about 20 SPECS commits during the window: new packages including cloudpods and cloudpods-operator (multi-cloud management platform), vkmark, assimp, glm, and kes; updates to go 1.27.1, jemalloc 5.4.0, iptables 1.8.13, flashrom 1.8.0, and libjaylink 0.5.0. On the container stack, it followed upstream repository migrations (address updates for podman, buildah, composefs, and containers-common), and allowed the riscv_hwprobe syscall in the default seccomp profile—this change lets programs inside containers probe RISC-V hardware features, with practical significance for cloud-native workload portability. Overall, the distribution is continuing to pile up packages in the “server and cloud-native” direction: cloud platforms, containers, and firmware tools are all being advanced simultaneously.

Official news page review: the latest entry remains “openRuyi 2026.08 released” (08-27); the 2026.09 version has not yet been released. Given the distribution’s monthly cadence (released in late each month), the September version has entered its release window and should be a key focus next issue.

1.4 openRuyi ceph-ci: Ceph RISC-V Porting Continues, precommit-hooks New Repo Lands

Date: 2026-09-18　Source: ceph-ci commit log, openruyi-precommit-hooks commit log

The openRuyi Ceph porting CI repository landed 8 commits during the window: introducing token authentication for pulling source from GitHub, resolving CI pull failures; applying a GCC 16 compatibility patch to rocksdb v9.11.2 (forcing inclusion of the cstdint header); upgrading lancedb to 0.39.0 on the rgw side while disabling lancedb by default on riscv64; and changing the CI flow to use dnf to install the built rpm into a clean base image for verification, replacing the previous manual checks. Separately, a new openruyi-precommit-hooks repository was established, with the first hook being an SPDX license header check, used to unify license declaration conventions for package submissions.

Ceph is a primary component of distributed storage, and its RISC-V porting and CI-ification mean the distribution has advanced another step toward “reproducible builds for the storage foundation.” Commits like the GCC 16 compatibility patch also suggest that openRuyi has begun to follow the pre-adaptation cadence of the next-generation toolchain.

II. Product and Ecosystem Developments

2.1 2026 Semiconductor Ecosystem Development Conference: RISC-V International Standard Timeline and BlueCore LX500 Commercial Progress

Date: Conference 2026-09-17 to 09-19 (Shanghai); report entered the window on 09-20　Source: Cailian Press / STAR Market Daily via East Money “Focus on the 2026 Semiconductor Ecosystem Development Conference: Industry Turns to Diversified Technological Breakthroughs, Space-Based Computing, 3D Packaging and RISC-V Flourish Across Multiple Fronts”

At the 2026 Semiconductor Ecosystem Development Conference held in Shanghai (theme: “AI Drives New Quality Chip Innovation”), RISC-V became an independent agenda track, with two pieces of industry information worth noting.

Standard timeline: Jiang Jiang, Executive President and Chief Technology Officer of Chaorui Technology (Shanghai), pointed out that the pain points of duplicated investment in AI industry operator libraries and fragmented ecosystems stem from the lack of unification between chip-level instruction sets and microarchitectures; RISC-V’s open standards, hardware-software decoupling, and open-source ecosystem are its three major advantages for becoming the underlying paradigm for AI chip innovation. Regarding the timeline for RISC-V to become an international standard, he offered the judgment that “the most optimistic estimate is approval by the end of 2027, while objectively it may take 2 to 3 years or even longer,” while emphasizing that this is an “irreversible major trend.”

Commercial progress: Jia Xinxia, Chief Technology Officer of BlueCore Computing (Shenzhen), disclosed that the company lit up its first RISC-V-based “intelligence-connectivity fusion” all-in-one CPU, the BlueCore LX500, in February this year, and based on this chip launched an agent all-in-one machine for AI-native scenarios; the product has completed adaptation for Qwen 3.5 35B (BF16 precision) and the Kimi K2.6 trillion-parameter large model, with adaptation for the Kimi K3 128K ultra-long context version underway. On the customer side, it has already landed with leading telecom operators, central and state-owned enterprise groups, cloud service providers, financial institutions, universities, and the industrial sector. Since 2026, it has secured batch orders domestically and internationally and begun deliveries, with some international cluster projects under construction.

2.2 SEMICON India 2026 Concludes: DIR-V Challenge Winners Announced, C-DAC Releases AI and Quantum Platforms

Date: 2026-09-19 to 09-20　Source: thepublicworld “SEMICON India 2026 Wraps up with 15 New Announcements on Chips, AI and Quantum Tech”, fintechbiznews “Digital India RISC-V Grand Challenge Won By 3 Teams” (Google News aggregation)

SEMICON India 2026 concluded, with RISC-V-related content occupying an important position among the 15 new announcements: the results of the Digital India RISC-V (DIR-V) Grand Challenge were revealed—the competition was organized by Maker Village under MeitY’s Chips to Startup (C2S) program, attracting a total of 1,236 teams and more than 5,000 participants, with three teams’ solutions sharing a prize pool of 600,000 rupees: first place went to SASTRA University’s autonomous surface cleaning robot based on the IIT Madras SHAKTI processor, second place to a digital stethoscope from Thiruvananthapuram (running on the C-DAC VEGA processor), and third place to IISc Bangalore’s forest monitoring system. All entries were based on India’s indigenous RISC-V processors (SHAKTI, VEGA), demonstrating that its domestic processor ecosystem is beginning to support practical application innovation.

Other announcements at the same event: C-DAC signed cooperation agreements with NLC India and Bharat Electronics respectively (energy industry data centers; high-performance computing, AI and sovereign data center solutions), and released PARAM Vidya (a plug-and-play AI experimentation platform for universities and startups) and PARAM Shavak-QS (a compact quantum simulation platform). On the market side, a joint report by EY and ISEA projects that India’s semiconductor market will grow from approximately $64 billion in 2026 to $200 billion by 2035.

2.3 Openchip: The Two-Year Tape-Out Path of Europe’s Sovereign RISC-V Chip BER10

Date: 2026-09-17 (first day of the window)　Source: RISC-V International “V Questions with… Openchip’s Cesc Guim and Marc Fernández”

The RISC-V International Foundation published an interview with two executives from Barcelona-based Openchip. BER10 is Europe’s self-developed high-performance RISC-V application processor based on open standards: the team was assembled from scratch in early 2024, with more than 350 employees across Spain, Italy, Poland, Belgium, France, Germany, and Ireland, completing tape-out in less than two years, and succeeding on the first attempt without requiring a re-spin. The chip is 64-bit, capable of running Linux, and integrates a vector unit, coherent fabric, memory and interconnect subsystems, and an independent management tile. On the funding side, it relies on €111 million in support from the IPCEI microelectronics project under the EU’s NextGenerationEU program.

Three key points from the interview: First, the chip successfully booted an operating system about three weeks after the silicon came back, and the team said the next “traditional ritual” is to run DOOM; second, the company’s positioning emphasizes “delivering systems” rather than just delivering chips—integration, certification, support, and a production-grade software stack are prerequisites for commercialization; third, it is in discussions with multiple European parties about a sovereign system stack based on seL4, taking “every layer verifiable” as the target form of European sovereign computing. This case is one of the most representative examples of the RISC-V path under Europe’s Chips Act framework.

2.4 Nordic Releases nRF54LC10A: A Multi-Protocol SoC with Cortex-M33 Plus RISC-V Coprocessor

Date: Released 2026-09-17, entered the window on 09-18　Source: LinuxGizmos “nRF54LC10A SoC features Cortex-M33, RISC-V coprocessor, Bluetooth LE, Thread and Zigbee”

Nordic Semiconductor has expanded its nRF54L series with a new entry-level multi-protocol SoC, the nRF54LC10A: a 128MHz Arm Cortex-M33 main core (with FPU, DSP, MPU, and TrustZone) + a 128MHz RISC-V coprocessor, the latter used for software-defined peripherals and offloading of time-critical tasks; 1MB NVM, 192KB RAM; a 2.4GHz radio supporting Bluetooth LE (including Channel Sounding), Thread, Zigbee, Matter, and proprietary modes (up to 4Mbps); available in three packages: CSP29, CSP39 (approximately 1.93 × 2.29mm), and QFN48. It is currently in early project-based sampling, with mass production expected in Q2 2027.

This is another example of RISC-V entering the mainstream IoT product lines of major international vendors as an “internal control core/coprocessor”: it exists alongside the main core without exposing a programming model externally, but with considerable shipment volumes—belonging to a different segment of the same penetration path as NVIDIA GPUs’ built-in RISC-V controllers.

III. Deep Dive on Domestic Teams

3.1 DAMO XuanTie: zero_stage_boot Releases XuanTie_V1.4.0 Stable

Date: 2026-09-18　Source: zero_stage_boot release page, damo-rv-priv-ats PR #32

DAMO XuanTie’s open-source zero-stage boot project zero_stage_boot released the XuanTie_V1.4.0 stable version on the evening of 09-18 (following three rounds of pre-releases: rc1, rc2, rc3). The release artifacts are a complete set of prebuilt packages: the zsb firmware itself, OpenSBI 0.9 and 1.7, and Linux 5.10 and 6.6 kernels, covering three ABI combinations — 32ilp32, 64ilp32, and 64lp64 (6.6 includes a debug variant) — targeting boot chain integration by downstream SoC vendors and board partners, so the “zero-stage boot — OpenSBI — Linux” chain runs out of the box on the corresponding XuanTie CPUs. The opensbi repository was pushed in the same batch.

Other activity in the same organization: the privileged-mode test repository damo-rv-priv-ats updated its test plan on 09-18, linking test items to specification clauses (PR #32), continuing its “tests aligned with specs” approach; the remaining 70-plus public repositories saw no pushes during the window, consistent with its recent focus on the boot chain and security testing.

3.2 SpacemiT: K3 Product Line Syncs Nearly 30 Repositories in Batch; ZJUT Kicks Off Semester with First Class at SpacemiT

Date: 2026-09-18　Source: spacemit-com organization push records, Tidenews, “On the First Day of School, ZJUT ‘Sent’ Students into a Chip Company”

Twenty-nine repositories in the SpacemiT spacemit-com organization saw pushes during the window, with nearly 30 repositories completing a batch push within one minute on the evening of 09-18 (spot-checking the linux-6.18 branch shows an update to the k3-br-v1.0.y product branch), covering the full K3 product line stack — buildroot, U-Boot, OpenSBI, Linux 6.18, Mesa, MPP, and VPU/GPU test tools. This is a typical batch sync of product branches, providing a unified baseline for downstream K3 platform integrators. No new version numbers were released by the organization during the window.

On the industry-education integration front: on 09-18, about 50 students from the School of Mathematical Sciences at Zhejiang University of Technology visited SpacemiT in Yuhang, Hangzhou on the first day of the semester, holding the first class of the new term on the company’s R&D front lines. A university organizing students to take their “first class” at a domestic chip company at the start of the semester reflects the normalization of Yangtze River Delta chip companies’ participation in local talent development. Combined with its full-stack investment in the K3 product line, such moves complement the company’s ecosystem and talent system strategy.

3.3 Sophgo: ZSBL Releases v3.2.0; sophon-tools Ships 2.1.x in Succession with f2fs Support

Date: 2026-09-18 ~ 09-20　Source: sophgo/zsbl commit history, sophgo/sophon-tools commit history

ZSBL (zero-stage boot) released v3.2.0 (09-18), one day after v3.1.0, incorporating two device model improvements: platform devices are now named by device tree path, and devices without drivers are no longer instantiated, making peripheral enumeration and identification friendlier for downstream distributions. The previous day also saw adjustments to version logic and removal of the platform version field, indicating the boot firmware is preparing for a round of multi-platform releases.

The psewriter component of the flashing tool sophon-tools shipped four versions in succession during the window, from 2.1.0 to 2.1.3: adding a “format TF card only” mode and making it the first option, embedding Chinese fonts to fix on-site garbled text, and fixing a startup failure caused by LVM_SETCOLUMNWIDTH. On 09-20 it added f2fs support (ota_update, socbak, and bmssm configurable per partition) and added file system type guards for the BOOT and recovery partitions — misconfiguring a partition type silently breaks the boot chain, and such “guardrail” commits show the tool moving from “can flash” toward “field delivery reliability.”

3.4 Sipeed: SLogic Logic Analyzer Software Stack Refactored, Shared Kernel Drivers and Three-Platform CI

Date: 2026-09-18 ~ 09-20　Source: sipeed/SLogic commit history, sipeed/slogic16u3-tools commit history

The Sipeed SLogic logic analyzer software stack completed a wave of architectural refactoring during the window: porting the libsigrok driver into the shared kernel, deduplicating the device table, splitting out a separate driver file for the Combo 8 model (slogic8u2.c), adding standardized export of display names for signal modes, and removing Windows rate-limiting logic from the shared kernel; on the CI side, it established full-product builds across three platforms (Windows/Linux/macOS, including Wine budget control). On the toolchain side: slogic16u3-tools added a Config tab (one-click configuration of WinUSB/udev environments), Chinese-English internationalization and an operations UI overhaul, a tag-triggered automated portable-edition release workflow, and fixes for capture crashes under GBK locale settings and module path issues in frozen Windows builds.

Previously (covered in the 09-17 issue), this toolchain had just completed flashing CLI sharing and libusb bundling; this issue represents the simultaneous advancement of “data acquisition-side kernel refactoring” and “application-side delivery polish,” as the toolchain converges toward a cross-platform, releasable engineering form.

3.5 Radxa Linkr: v1.5.0 Released, Plugin Center and Network Plugins Launch

Date: 2026-09-18　Source: radxa-linkr/linkr Releases

Radxa’s browser-based remote management product Linkr released v1.5.0 (about two weeks after v1.4.2). New features: a plugin center — a unified entry point for uploading, installing, enabling, disabling, and uninstalling plugins; ZeroTier and EasyTier network plugins — supporting joining a network, viewing network information, and leaving a network; screenshot watermarks that adapt to screenshot dimensions; OCR text recognition — results are editable and copyable, with support for offline operation via plugins; experimental IPv6 support; and Agent API support for switching resolution and video quality. Improvements and fixes: keyboard compatibility and input latency, prompts and manual recovery when audio playback is blocked, and Tailscale switching to the REST API with a warning about conflicts with ZeroTier.

Linkr targets remote management scenarios for development boards and NAS devices. This release centers on an “extensible plugin system,” an important signal of its evolution from a standalone tool to a platform product — the plugin-based network channels (ZeroTier/EasyTier/Tailscale) are especially suited to remote operations scenarios.

3.6 Member Website Sweep: 391 Completed, No Confirmable Substantive Developments Found

Date: 2026-09-21 verification　Source: RISC-V International member company websites (391 total, Premier 20 / Strategic 169 / Community 202)

This window completed a sweep of all 391 member company websites: 269 unchanged, 52 with body-text changes, and 70 failed to fetch. Most changes were homepage marketing carousels and news tickers (NVIDIA GTC Washington preview, AMD, Codasip, MIPS, SUSE, Seagate, OpenHW Foundation, plus university pages such as MIT, Berkeley, and UNSW); after item-by-item review, no substantive developments confirmable as new product releases, funding, architecture releases, or partnerships were found, and no items are included from member website channels in this issue. Fetch failures were mainly domestic sites and anti-scraping sites (Institute of Software, Chinese Academy of Sciences; Beijing Institute of Open Source Chip; Xinsiyuan; Andes; Tencent; ADI; etc.); failures do not block the sweep process.

IV. Embodied Intelligence and Robotics Special Section

4.1 Suzhou Ruixin × Qiyuan Robot: High-Light D35 Dataflow Physical AI Chip Enters the Humanoid Robot Ecosystem

Date: 2026-09-20 (mass production news 09-14)　Source: Shanghai Securities News via Sina Finance “Ruixin RISC-V Dataflow Physical AI Chip Partners with Qiyuan Robot”, GeekPark “Qiyuan Robot Launches Q1/T1 Dual New Products, Officially Announces Suzhou Ruixin as Computing Ecosystem Partner”, Suzhou Industrial Park “RISC-V Dataflow Physical AI Chip Goes into Mass Production!”

Shangwei New Materials (688585)’s consumer-grade embodied intelligence brand Qiyuan Robot launched two personal robots, Q1 and T1 (starting at 19,999 yuan), in Shanghai on 09-20, and officially announced Suzhou Ruixin Integrated Circuits as its computing ecosystem partner: the two parties will conduct technical cooperation around the edge-side computing needs of embodied intelligence, advancing the deployment of dataflow-architecture AI chips in humanoid robot scenarios.

Founded in 2020, Suzhou Ruixin takes a differentiated route of “RISC-V instruction set + dataflow architecture”: it holds more than 80 dataflow patents, its core team comes from institutions including the Institute of Computing Technology of the Chinese Academy of Sciences, the Institute of Automation of the Chinese Academy of Sciences, IBM, and Intel, and its research results received an ISCA 2026 Best Paper nomination; its fully self-developed RISC-V CPU core IP has passed technical certification by an international semiconductor giant and entered the global procurement system. Its flagship product, High-Light D35, is positioned as “the world’s first RISC-V dataflow physical AI chip”—triggering computation on data arrival to reduce the energy consumption and latency of data movement, focused on edge-side inference, with a single chip supporting up to 128GB of high-speed video memory, adopting Chiplet advanced packaging and a full-stack software toolchain, and was announced for mass production by Suzhou Industrial Park in mid-September. The launch event displayed the D35 chip itself and controller modules in the ecosystem exhibition area.

Significance and boundaries: This is the first time a domestic RISC-V chip has entered the stage of a consumer-grade humanoid robot launch event as a “computing ecosystem partner”; however, the cooperation is currently at the stage of “technical cooperation and deployment exploration,” and the actual installation form and mass production pace of D35 in Qiyuan products remain to be disclosed later. The chip parameters in the reports are all quoted from the manufacturer’s statements.

4.2 SpacemiT spacemit-robotics: ORB-SLAM3 Runtime Repository and Usage Guide Landed

Date: 2026-09-20　Source: ros2_orbslam3_run repository, docs-ros PR #208, manifest commit history

spacemit-robotics imported the ORB-SLAM3 runtime repository (ros2_orbslam3_run) on 09-20: the first commit already includes the ability to load camera calibration from CameraInfo and TF; the accompanying manifest repository added this runtime repository to the workspace manifest, and the docs-ros documentation repository simultaneously merged in the ORB-SLAM3 usage guide (PR #208). ORB-SLAM3 is a classic open-source implementation of visual SLAM, supporting monocular/stereo/inertial multimodality. This integration in the standard form of a “repository + manifest + documentation” trio means that visual mapping and localization capabilities are being formally incorporated into the K3 robot software stack, a step in completing the perception chain of the spatial computing platform.

4.3 SpacemiT spacemit-robotics: ros2_humanoid Adds ZMQ Policy Switching and Voice Control

Date: 2026-09-18　Source: ros2_humanoid commit history

ros2_humanoid landed three human-machine interaction enhancements in succession on the same day: adding ZMQ control and policy switching (10:33), voice control for standing actions (11:11), and switching humanoid policies via ZMQ commands (11:55). Previously, the repository’s main line was connecting ROS 2 with its self-developed motion control stack (velocity command integration, cmd_vel velocity bias, transport layer V2 migration); this issue abstracts “policy switching” into a capability that can be issued via ZMQ and introduces a voice entry point, indicating that the humanoid development platform continues to broaden its functional surface in human-machine interfaces and multi-policy management—moving from “being able to control” toward “multiple control channels and runtime switching.”

4.4 Sophgo sophon-demo: π0.5 VLA Porting Example and CV84X6 Batch Adaptation

Date: 2026-09-19　Source: sophon-demo release branch commit history

Sophgo’s sophon-demo merged a π0.5 VLA porting example into the release branch (targeting the BM1684X SoC, 09-19): porting Physical Intelligence’s π0.5 vision-language-action model to its own edge inference platform. This is a key move by its example library toward the embodied intelligence model side after large language models (LLM-TPU), providing robot customers with an out-of-the-box runnable VLA reference implementation. The same batch of commits completed batch adaptation for the CV84X6 (SE13-64) form factor: 11 detection/tracking examples, as well as generative examples including FLUX.1, Stable Diffusion XL/1.5, Seamless, and ChatTTS. At this point, the example library has CV84X6 support across all three load categories of “perception-generation-action,” reflecting that Sophgo’s software support for the new-generation packaging form factor has basically taken shape.

V. Summary and Trend Observations

  • The largest single domestic RISC-V financing round appears on the capital side: Yixing Intelligence raised nearly 2 billion yuan at a post-investment valuation of nearly 15 billion yuan, compounded by Suzhou Ruixin’s High-Light D35 entering mass production and partnering with Qiyuan Robot, and Lanxin Computing’s LX500 customer deployment—two high-value tracks, cloud computing and embodied intelligence, simultaneously obtained “commercialization evidence.” Compared with the “technology validation” narrative half a year ago, the key variable going forward is delivery and order fulfillment; the vote of confidence implied by the valuation needs to be repaid with revenue.
  • Standards and ecosystem rhythms proceed in parallel: Chaorui Technology gives the RISC-V international standard a “most optimistic by end of 2027” timetable, echoing the launch of domestic automotive QC/T standard drafting in previous issues; standard cycles are measured in years, while product launches are measured in months, and the rhythm gap between these two lines is key to understanding industry expectations.
  • The “serverization” of the open-source software side advances steadily: commits such as openRuyi’s cloudpods, the container stack’s seccomp allowing riscv_hwprobe, and Ceph porting CI are all foundational work to move server-grade workloads onto RISC-V; the openRuyi September release has entered its release window and will be a key focus next issue.
  • The technical content of the XiangShan ecosystem this week is concentrated in AME matrix extensions: NEMU/difftest successively landed matrix extension boundary behavior and differential adaptation, paired with a branch-level store prefetch optimization queue; matrix computation and memory access optimization are its recent main thrust.
  • Domestic vendors’ engineering main lines each have their own emphasis: DAMO XuanTie released the complete ZSB firmware set (boot chain); Sophgo rapidly iterates ZSBL and flashing tools (delivery reliability); Sipeed refactored the SLogic software stack (tool platformization); SpacemiT batch-synced K3 branches and deepened its robot software stack (ORB-SLAM3, human-machine interfaces); Radxa Linkr shifts toward a platform product with a plugin system.
  • Limitations note: The data in this issue comes from public web pages and public GitHub commits, with no non-public channels used. The unauthenticated GitHub API was near its rate limit during the collection period, and some repositories’ commit details were cross-verified via Atom feeds and the events API; the RISC-V International Foundation membership website inspection had 70 failed fetches (mainly domestic sites and anti-scraping sites); conference-related information (Semiconductor Ecosystem Development Conference, SEMICON India) comes from aggregator channels, with conference dates already noted.
  • Next issue’s focus: whether the openRuyi 2026.09 release is published (including container and cloud-native stack updates); the delivery pace of Yixing Intelligence’s new-generation chips and supernodes; the specific deployment form of the Suzhou Ruixin and Qiyuan Robot cooperation; the merge trends of XiangShan’s various optimization branches; whether DAMO XuanTie’s toolchain and kernel repositories resume pushing.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News Hit an XDA article on NVIDIA GPUs with built-in RISC-V cores (09-20, 45 points) — this article was already covered in the 09-17 issue, so it is not repeated here; no other entries had strongly RISC-V-related new posts
Google News aggregation (multiple Chinese and English query sets) On the English side, hits included the Yixing financing (multiple articles in multiple languages), three SEMICON India items, and the Semiconductor Ecosystem Development Conference; on the Chinese side, hits included Ruixin × Qiyuan, the Qiyuan launch event, and ZJUT × Intespace; gambling, stock market, and sports noise was removed in bulk by semantics
Chinese industry media (Shanghai Securities News / Cailianshe / Lieyunwang / GeekPark / Tide News / Gasgoo) Hits included the Yixing financing, Ruixin × Qiyuan, Lanxin LX500, the Chaorui standard timetable, and the ZJUT first-day-of-school class; the DAMO Academy Li Weili automotive-grade report was a secondary reprint of 09-16 conference content (already covered in the 09-18 issue) and was not repeated
GitHub organizations and key repositories Pushes within the window: XUANTIE-RV 3 repos, sophgo 7 repos, spacemit-com 29 repos, spacemit-robotics 3 repos, sipeed 4 repos, radxa-linkr 1 repo, openRuyi-Project 4 repos, XiangShan family 5 repos, espressif 46 repos (mostly Xtensa platform and general components, with no version-level activity, so not included as RISC-V); no pushes: eswincomputing, Nuclei-Software, revyos (latest push 09-18 04:28, outside the window), openhwgroup
RISC-V International official website / member official websites The latest entry on the official News page is still 08-21; 391 member official websites were swept (269 unchanged / 52 changed / 70 failed), and no substantive activity was found
openRuyi official website / GitHub The latest item on the official news page is still the 2026.08 release (08-27), and the September version has not been released; GitHub repository SPECS commits are active (about 20 items), with ceph-ci and precommit-hooks advancing in parallel
CNX Software / LinuxGizmos / Phoronix RSS Hit nRF54LC10A (included), OpenMote remote control (ESP32-S3 uses an Xtensa core, not RISC-V, removed), and no other entries within the window