Research window: Past 24 hours (2026-09-21 05:00 ~ 2026-09-22 05:00, Beijing time). Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), Yicai, Sina Finance, Phoenix Net / Wangtongshe, China Science and Technology Net (Science and Technology Daily), CCID Net, Xindongxi, OSChina, EE Times, Machine Maker, openRuyi official news page, RISC-V International Foundation member company website sweep (391 companies), and GitHub (XiangShan / NEMU / GEM5 / difftest / XSCache, openRuyi-Project, ESWIN, Sophgo, SpacemiT, Sipeed, revyos, Espressif and other organizations’ and key repositories’ push and commit searches)

Index

  • Today’s Highlight: ESWIN passes HKEX listing hearing, poised to become Hong Kong’s “first RISC-V stock” (09-21)
  • I. Open-Source Community and Software Ecosystem
    • openRuyi: Kernel dual-track upgrade to 7.2.6 and 6.18.52, batch security fixes land (09-21)
    • XiangShan: Kunminghu V3 branch fixes CBO and prefetch paths, NEMU makes mseccfg configurable (09-21)
    • Bluespec open-source hardware IP library Tape-Out (FukuzSoC) batch of new repositories (09-21)
    • simdjson sees experimental RVV vector backend repository (09-21)
    • Open-source ecosystem briefs: GNOME Flatpak riscv64 build, Exercism track and AG32 open-source toolchain (09-21)
    • Beijing Open-Source Innovation Competition adds open-source intelligent hardware track, to be held in November alongside GOTC 2026 (09-21)
  • II. Product and Ecosystem Developments
    • India’s Aheesa releases VIHAAN-I: domestically developed RISC-V broadband network SoC completes tape-out (09-21)
    • Smart Automotive Chip Ecosystem Conference follow-up: DF30 plans volume production in 2026, Infineon’s next-generation automotive MCU fully pivots to RISC-V (09-21 report)
    • IC WORLD Conference RISC-V Open Computing Forum: Telecom’s “Beihai” platform, Sophgo server CPU and openKylin adaptation progress (09-21 report)
  • III. Deep Dive on Domestic Teams
    • ESWIN: EIC7X release branch and eic7700_sample new repository land (09-21)
    • Sophgo: sophon-tools batch fixes and Qwen3 series CV84X6 bmodel (09-21)
    • SpacemiT: model-zoo-vision RVV preprocessing fusion optimization and mpp update (09-21)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • SpacemiT spacemit-robotics: humanoid robot joint configuration fixes and remote control receiver component merged (09-21)
    • 2026 Global AI Chip Summit: SpacemiT discloses “brain-cerebellum fusion chip” plans (09-21)
  • V. Summary and Trend Observations

Today’s Highlight: ESWIN passes HKEX listing hearing, poised to become Hong Kong’s “first RISC-V stock”

Date: 2026-09-21　Sources: Yicai “ESWIN Passes HKEX Listing Hearing”, Sina Finance / Guandian Net “ESWIN Passes HKEX Listing Hearing, 2025 Revenue 2.431 Billion Yuan”, NetEase “ESWIN Passes HKEX Hearing, RISC-V Track Poised to Welcome ‘First Stock’”

According to HKEX documents, Beijing ESWIN Computing Technology Co., Ltd. passed the HKEX Main Board listing hearing on 09-21, with joint sponsors CITIC Securities and CITIC Securities International (the company filed its prospectus for the third time on 2026-07-31). If the subsequent offering proceeds smoothly, it will become Hong Kong’s “first RISC-V stock,” filling the gap in listed targets in the RISC-V chip track.

Operating data: The company adopts a Fabless model, with RISC-V as its technology foundation, and its products cover human-machine interaction and multimedia processing chips, interconnect and computing chips, focusing on two major scenarios: intelligent terminals and embodied intelligence; revenue from 2023 to 2025 was 1.752 billion yuan, 2.025 billion yuan, and 2.431 billion yuan respectively, with a net loss of 1.516 billion yuan in 2025; Q1 2026 revenue was 494 million yuan (up 18.4% year-on-year), net loss 375 million yuan, gross margin 14.8%. As of March 31, 2026, it has launched over 150 software-hardware co-designed products, serving more than 220 customers globally; computing product revenue grew from 375,000 yuan in 2023 to 320 million yuan in 2025, reaching 223 million yuan in Q1 2026, with products entering core tracks such as automotive and industrial. Based on 2025 revenue, the company is the largest domestic provider of intelligent terminal human-machine interaction chips.

Industry data was also released: According to Frost & Sullivan, China’s RISC-V main control chip market grew from 1.1 billion yuan in 2021 to 37.7 billion yuan in 2025 (CAGR 139.5%), and is expected to expand to 219.4 billion yuan by 2030. The boundary to keep in mind: passing the hearing still leaves process before formal issuance and pricing, and the company’s net loss and the ramp-up pace of its computing product line will be the most direct test indicators after listing. On the same day, the company had a corresponding release action on GitHub (see 3.1).

I. Open-Source Community and Software Ecosystem

1.1 openRuyi: Kernel dual-track upgrade to 7.2.6 and 6.18.52, security fixes land in batch

Date: 2026-09-21　Source: openRuyi commit: linux upgrade 7.2.6, kernel-team-tools: TAG bumped to v7.2.6-1, openRuyi official news page

Within the rolling-release window, openRuyi landed more than 20 commits, centered on the kernel dual-track upgrade and upstream follow-up: linux upgraded to 7.2.6 and linux-lts to 6.18.52 (both with patchset and config refreshes); kernel-team-tools updated the build tags for four kernel series (6.18.52-1 / 7.0.14-5 / 7.1.13-1 / 7.2.6-1) and enabled options including ULTRARISC, VFIO_IOMMU_TYPE1, and ARCH_ANLOGIC in the kernel config; the ruyi/6.18.y, 7.0.y, 7.1.y, and 7.2.y maintenance branches of openRuyi-Project/linux were all pushed the same day.

On the build-system side: a new openruyi-linux-build component was added (providing a unified linux package for all flavor variants); the three specs linux / linux-lts / linux-lts-kmhv2 were switched to unified maintenance via rpm macros; glibc 2.44 caught up with the upstream snapshot. Security and package updates landed in batch: python-pytorch-lightning 2.6.6, python-datasets 5.0.1, python-ujson 6.0.0, ImageMagick 7.1.2.31, pcre2 10.48 (all commits tagged security-fixes); on the cloud-native side, Go packages such as k8s konnectivity-client and kms, Datadog dd-trace-go, and VictoriaMetrics were added. There were no new announcements on the official news page during the window, and the September release has not yet shipped (the latest is 2026.08, released 08-27).

1.2 XiangShan: Kunminghu V3 branch fixes CBO and prefetch paths, NEMU makes mseccfg configurable

Date: 2026-09-21　Source: XiangShan commit: LoadUnit retains prefetch.i retirement path (#6230), NEMU commit: mseccfg made a Kconfig option (#1221)

The five commits in the main XiangShan repository during the window all landed on the kunminghu-v3 branch: LoadUnit now lets prefetch.i retire normally instead of clearing it in the S1 stage (#6230); two fixes for CBO (Cache Block Operation) instructions — numWb changed to 2 in the decode stage, and StoreQueue credits in the Load-Store Queue are now correctly preserved across CBO lanes; the docker base image was switched to xs-env:stable (#6577); on the CI side, ckpt_select.py was improved and nightly fuzz was added (#6604). On the NEMU side, two items: mseccfg was made a Kconfig option (#1221), and the virtualization supervisor timer is now disabled only when nemu_timer is enabled.

Branch-level development in GEM5 is equally active: the feat-ywl-pfbuffer branch added a PDB (prefetch data buffer) model and fixed its replay-cleanup and prefetch-admission logic; during the window, new development branches such as Hybrid_CROB and calibrate-rvv-iq were also opened (targeting a hybrid CROB and RVV instruction-queue calibration, respectively). There were no new commits on the difftest and XSCache main branches during the window; mainline merge activity remains to be seen.

1.3 Bluespec open-source hardware IP library Tape-Out (FukuzSoC) opens repositories in batch

Date: 2026-09-21　Source: GitHub organization Tape-Out (FukuzSoC)

An open-source hardware IP library named FukuzSoC opened repositories in batch on 09-21, including three reference SoCs (soc-mcu / soc-linux / soc-smp) and a PLIC interrupt controller, among others. The organization describes itself as “an open-source hardware IP library built with Bluespec and assembled by the XiRang package manager”: each IP repository contains ip.yaml (configuration options, contracts, and measured area), regmap.yaml (register map), Bluespec source, and behavioral tests covering the full configuration matrix; the in-house toolchain xirang handles parsing, generation, testing, and “pricing,” with spec files defining semantics.

The IP lineage covers hart processor cores, caches, NPU / GPGPU / YOLO accelerators, RISC-V interrupt-system components such as ACLINT / PLIC / IMSIC, peripherals such as UART / SPI / I2C, and Ethernet switch / routing modules; maturity is divided into five levels — planned / simulated / fpga-proven / asic-ready / silicon-proven — displayed as a badge in each repository. The reference SoCs explicitly “contain no proprietary RTL” and are assembled entirely from IP — this “package manager + IP library” organizational approach differs from the common domestic single-repository RTL model, and its maturity progression is worth tracking. (Note: it is a recently publicized project, with no public tape-out record or community discussion yet.)

1.4 simdjson gains an experimental RVV vector backend repository

Date: 2026-09-21　Source: MA-Gustave/Simdjson-rvv-vla

A developer open-sourced an experimental RISC-V vector (RVV 1.0) backend for simdjson, written in a vector-length-agnostic (VLA) style, with accompanying GCC / Clang validation, runtime dispatch, upstream acceptance tests, and reproducible performance benchmarks; the repository was created on 09-21 with commits pushed continuously the same day. simdjson is a widely used high-performance JSON parsing library, and if the RVV backend is accepted upstream, it will fill in the vector acceleration path for this library on the RISC-V platform. Note: it is currently a personal experimental repository at an early stage, and both performance and upstream acceptance progress remain to be verified.

1.5 Open-source ecosystem briefs: GNOME Flatpak riscv64 builds, Exercism track, and AG32 open-source toolchain

Date: 2026-09-21　Source: nico359/gnome-flatpak-riscv64, Exercism RISC-V track, bbenchoff/AGaMEMnon

Three lightweight updates: first, a developer maintains an unofficial riscv64 build repository for the GNOME Flatpak Platform / SDK (created 09-11, continuously updated during the window); if it matures, it will improve distribution conditions for containerized applications on the RISC-V desktop; second, the Exercism programming-learning platform opened a RISC-V track (with a standalone test-runner, pushed 09-21), bringing RISC-V into the platform’s language list; third, AGaMEMnon (48 stars, an open-source flow based on yosys / nextpnr), the open-source SDK and toolchain project for AG32 (an AGM Semiconductor RISC-V MCU with embedded AGRV2K FPGA logic), was active during the window, continuing to advance open-source tool support for this “MCU + FPGA” hybrid chip.

1.6 Beijing Open-Source Innovation Competition adds an open-source intelligent hardware track, to be held in November alongside GOTC 2026

Date: 2026-09-21　Source: OSChina, “From embodied intelligence to desktop gadgets, Beijing Open-Source Innovation Competition hardware track opens to makers nationwide”

Registration is open for the 4th OpenAtom Competition · 2026 Open-Source Industry Solution Innovation Competition (Beijing Open-Source Innovation Competition): it features a dedicated “Open-Source Intelligent Hardware Solution” track, soliciting integrated hardware-software solutions such as intelligent terminals, embedded systems, IoT devices, and embodied-intelligence hardware, covering form factors including industrial handheld terminals, medical terminals, robots, and wearables; control programs must be open-sourced and structural parts must have public 3D model drawings so others can reproduce them. Registration and material submission close on October 31, and the finals will be held on November 13–14 in Beijing Yizhuang, where 30 teams will compete for a total prize pool of 1 million yuan; entries may be exhibited at the GOTC 2026 Global Open-Source Technology Summit on November 14 (expected 3,000 attendees and 100 market stalls). In the competition’s introduction, RISC-V is listed alongside Arduino and 3D printing as a foundational force in the open-source hardware ecosystem.

II. Product and Ecosystem Updates

2.1 India’s Aheesa Unveils VIHAAN-I: Indigenous RISC-V Broadband Networking SoC Taped Out

Date: 2026-09-21　Source: EE Times, “Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC”, Machine Maker, “Aheesa Advances India’s Semiconductor Ambitions with Indigenous VIHAAN Broadband Networking Chip”

Chennai-based fabless startup Aheesa Digital Innovations showcased its in-house RISC-V broadband networking SoC VIHAAN-I during SEMICON India 2026 (the company bills it as India’s first indigenously designed RISC-V broadband networking chip). The chip uses a 28nm process and integrates compute, broadband access, and system control on a single die, targeting GPON/EPON fiber access and telecom infrastructure, with the goal of replacing imported semiconductors in India’s telecom and networking sector. The company has completed VIHAAN-I tape-out, plans to move to multi-project wafer (MPW) manufacturing, and targets commercialization in Q1 2027; the project has been recognized under India’s MeitY Design Linked Incentive (DLI) scheme and received seed funding from Tamil Nadu’s Emerging Sector Seed Fund. Significance and caveats: this is the first RISC-V SoC vehicle for India’s “domestic chip” agenda in the telecom infrastructure segment, but the product is not yet in mass production, and process and performance details come solely from vendor and trade-show accounts.

2.2 Smart Vehicle Chip Ecosystem Conference Follow-up: DF30 Targets Volume Production in 2026, Infineon’s Next-Gen Automotive MCUs Shift Fully to RISC-V

Date: 2026-09-21 (conference 09-16)　Source: Phoenix News via AutoNet, “2026 6th Smart Vehicle Chip Ecosystem Conference Held; Dongfeng, Changan, SAIC, Infineon and Others Discuss RISC-V Architecture Applications”, Phoenix News via AutoNet, “Infineon Announces Next-Generation Automotive MCUs Shift Fully to RISC-V Architecture”

On 09-21, AutoNet published two follow-up reports on the 2026 6th Smart Vehicle Chip Ecosystem Conference, filling in details not previously covered. First, Dongfeng Motor disclosed quantitative milestones for its RISC-V automotive-grade chip: DF30, jointly developed with China Information and Communication Technologies Group (CICT) and involving Wuhan Binary Semiconductor, is based on a RISC-V multi-core architecture, a domestic 40nm automotive-grade process, and ASIL-D functional safety; since its November 2024 launch, it has completed validation in Dongfeng models including the eπ 007, M-Hero M817, and Aeolus Haohan, debuting in engine ECUs, with volume production planned for 2026 and the first production vehicles with the chip rolling off the line by year-end; Nuclei, which supplies the CPU cores, has grown its team from just over 20 to roughly 500 people, and the chip has completed more than 600 tests.

Second, an Infineon automotive executive outlined the company’s “next-generation automotive MCUs shifting fully to RISC-V” strategy at the conference: new products will join the AURIX family (coexisting with TriCore and Arm lines), and its automotive MCU share has risen from 32.1% in 2025 to 36%; in March 2026 it released the DRIVECORE virtual prototype evaluation package, already used by some domestic OEMs and Tier 1s for early evaluation; on the AUTOSAR side it is working with Vector, Neusoft Reach, and Purhua on adaptation, while on the open-source side it is advancing FreeRTOS/Zephyr/NuttX; it has also joined the automotive RISC-V working group of the China Automotive Chip Standards, Testing and Certification Alliance (CACC) as a core member. Industry figures: RISC-V penetration in automotive is expected to rise from about 10% in 2025-2026 to 31% by 2031; Mobileye EyeQ Ultra has integrated 12 RISC-V cores and is entering its volume production window, while Horizon Journey 6 also partially adopts RISC-V cores in mass production.

2.3 IC WORLD RISC-V Open Computing Forum: Telecom “Beihai” Platform, Sophgo Server CPU, and openKylin Adaptation Progress

Date: Reported 2026-09-21 (conference 09-16 to 09-18)　Source: China Science and Technology Network (Science and Technology Daily), “2026 Beijing Microelectronics International Symposium and IC WORLD Conference Held in Yizhuang”, CCIDnet, “Helping RISC-V Move from ‘Usable’ to ‘Easy to Use,’ RISC-V Open Computing Forum Successfully Held in Beijing”, OSChina, “openKylin Appears at 2026 IC WORLD Conference, Jointly Exploring RISC-V Computing Ecosystem Development”

Details of the “RISC-V Open Computing Forum: Embodied Intelligence · Large Models · Data Centers” at the 2026 Beijing Microelectronics International Symposium and IC WORLD Conference (09-16 to 09-18, Yizhuang) were further disclosed within the window (OSChina published its openKylin attendance piece on 09-21). The forum was hosted by the Beijing Integrated Circuit Society and the RDI Alliance, and organized by the Beijing RDI Innovation Center: ESWIN Computing vice president Liu Shuai said RISC-V shipment growth has outpaced x86 and Arm, and the company continues to build RISC-V core components and solutions; China Telecom Research Institute presented achievements in building the “Beihai” RISC-V intelligent computing platform, while flagging two bottlenecks—difficult software ecosystem adaptation and insufficient validation of large-scale clusters; Wuhan Yuanshi Intelligent Computing proposed prioritizing storage and management scenarios to achieve unified cross-architecture computing scheduling; the openKylin community presented its progress in hardware adaptation, AI capability integration, cloud-native support, and embodied intelligence scenarios; Beijing Sophgo showcased deployment cases of its mass-produced RISC-V server CPUs in intelligent computing centers, government cloud, and other scenarios; Qingdao Guoshi Information shared a construction plan for a marine trusted data space supported by RISC-V; and the Beijing RDI Innovation Center said it will next build a RISC-V intelligent computing foundation validation system and lay out embodied intelligence edge controllers.

III. Deep Dive into Domestic Teams

3.1 ESWIN Computing: EIC7X Release Branch and New eic7700_sample Repo

Date: 2026-09-21　Source: eswincomputing/u-boot new release-EIC7X-2026.06 branch, eswincomputing/linux-stable branch of the same name, eic7700_sample first commit

On the same day as its HKEX hearing, ESWIN Computing made three moves on GitHub: the u-boot and linux-stable repos each created a release-EIC7X-2026.06 release branch (recent commits on the linux-stable branch include a batch of fixes for the ESWIN ISP media subsystem — frame rate recovery, ISP restart, imx415 and dvp2axi corrections — plus RISC-V DTS additions; the u-boot branch includes kernel-stage HDMI display fixes, eMMC partition and board-level information corrections), and a new eic7700_sample repo was opened (first commit that day). Establishing a release branch for EIC7X (corresponding to the EIC7700 series edge computing SoCs) typically signals version freeze and preparation for customer release, corroborating the timing of the hearing — capital moves and engineering delivery proceeding in parallel within the same week is a signal of its shift from “IP and chip supplier” to a mass-production delivery cadence.

3.2 Sophgo: Batch of sophon-tools Fixes and Qwen3 Series CV84X6 bmodels

Date: 2026-09-21　Source: sophon-tools #200: VPSS utilization capture (v1.6.0), LLM-TPU: Qwen3 series CV84X6 bmodels, sophon-demo: Qwen3.5 prefix cache fix

Sophgo advanced on three fronts simultaneously: six commits/merges in sophon-tools during the window — get_info adds VPSS per-component utilization capture for bm1688/cv186ah/cv84x6 (v1.6.0), fixes CV84X2 NIC name determination (distinguishing WAN/LAN by ascending register base address), fixes a broken RECOVERY f2fs guard in the bm1684 embedded packaging chain, byte-aligns three same-origin copies of socbak/bmssm to v1.5.8, and filters performance history exports by web checkbox selections while adding dates to chart x-axes; LLM-TPU adds bmodels for Qwen3-Embedding and Qwen3-TTS on CV84X6; sophon-demo fixes Qwen3.5 prefix cache issues (roughly 3 percentage points of accuracy loss and non-determinism, three fixes). The density of fixes across the toolchain, model assets, and demo library lines shows that software support for its new-generation package formats (CV84X6/SE13-64) is still being rapidly filled in.

3.3 SpacemiT: RVV Preprocessing Fusion Optimization in model-zoo-vision and mpp Update

Date: 2026-09-21　Source: model-zoo-vision #86: RVV-accelerated fused CPU pack, mpp: stream packets passed by VB reference, ai-sdk submodule update

SpacemiT’s vision model library model-zoo-vision merged four optimization PRs in a single day, with the main thrust being RISC-V Vector extension (RVV) acceleration of image preprocessing: first RVV-accelerating the fused CPU pack (#86), then migrating the face/clip models to the fused pack (#87), followed by fusing the tracking pack with RVV OCR recognition (#88), and finally extracting shared RVV u8c3 pack helper functions to complete the refactor (#89). In the same window, mpp (the multimedia processing platform) added “stream packets passed by VB reference” on a feat branch and filled in tests plus cpplint style fixes; ai-sdk updated the vision submodule twice. Preprocessing is a classically CPU-intensive stage in CV pipelines, and this group of commits continues its optimization habit of “moving operators from generic CPU paths to RVV.”

IV. Embodied Intelligence and Robotics Special Section

4.1 SpacemiT spacemit-robotics: Humanoid Robot Joint Configuration Fix and RC Receiver Component Onboarding

Date: 2026-09-21　Source: humanoid_linglong PR #13: Hip Joint Configuration Fix, peripherals-rc_receiver: Event-Driven Callback Lifecycle, manifest: Add RC Receiver Component

Three advances within the spacemit-robotics organization window: First, the humanoid robot project humanoid_linglong merged a hip joint-related fix (correcting hip motor configuration, retaining hip damping from the legacy policy), pointing to joint calibration issues during real-machine debugging. Second, the new RC receiver peripheral component peripherals-rc_receiver submitted event-driven callback lifecycle alignment and was formally incorporated into the robot component build system via manifest (the manifest had already been continuously expanding in previous windows). Third, the visual mapping project linksee cleaned up unused occupancy grid nodes (#25). From the ORB-SLAM3 runtime repository and ros2_humanoid to the joint and RC peripheral work in this window, its robotics software stack continues to be filled in block by block following a “componentization + manifest assembly” rhythm.

4.2 2026 Global AI Chip Summit: SpacemiT Discloses “Brain-Cerebellum Fusion Chip” Plans

Date: 2026-09-21　Source: Chip Insights “Want to See Where AI Chips Go Next? If You Missed the Shanghai Summit, This One Article Is Enough”

According to a 09-21 report by Chip Insights, the 2026 Global AI Chip Summit (Shanghai, two days) concluded, with over 60 speakers and more than 100 AI chip ecosystem companies in attendance. RISC-V-related highlights centered on SpacemiT: its Chip Product Director Chen Jiandong described advancing “isomorphic fusion computing” based on RISC-V—using a unified architecture, unified memory, and unified software system to achieve on-demand allocation of CPU compute, AI compute, and real-time compute; two generations of chips have already entered mass production, with K1 as the first generation (2T AI compute) and K3 as an eight-core CPU (2.4GHz main frequency, 60T AI compute, supporting deployment of 30B models), with a higher-compute-platform “brain-cerebellum fusion chip” to be developed subsequently. On the exhibition side, Nuclei, Imagination, SpacemiT, and other companies displayed product solutions; at the embodied intelligence chip forum, Weifan Intelligence proposed a BiGPU biomimetic brain-inspired architecture for embodied scenarios. The summit took “from TOPS to Token” as its main thread, reflecting that the industry’s focus is shifting from peak compute to software-hardware co-design in inference scenarios.

V. Summary and Trend Observations

  • The capital market delivers the “first RISC-V stock”: ESWIN Computing passed the Hong Kong Stock Exchange hearing, with 2025 revenue of 2.431 billion yuan, and computing product line revenue growing from 375,000 yuan in 2023 to 320 million yuan in 2025—more meaningful as a test than the IPO narrative is the slope of the computing chip revenue curve; on the same day, its EIC7X release branch and example repository landed, marking the first time capital moves and engineering delivery formed a contrast within the same week.
  • Automotive-grade RISC-V moves from “discussion” to the “mass production list”: DF30 plans large-scale mass production in 2026, with the first batch of equipped vehicles rolling off the line by year-end, and Nuclei’s core team expanding to about 500 people; Infineon (36% automotive MCU share) is shifting its next-generation automotive-grade MCUs entirely to RISC-V. Domestic automakers and international giants converge on the same timeline, with 2026 to 2028 seen as the critical three years for electronic/electrical architecture transition.
  • The “supply side” of the open-source ecosystem continues to thicken: openRuyi kernel dual-track upgrades and security batching, XiangShan Kunminghu V3 and GEM5 branch-level fixes, the Bluespec open-source IP library Tape-Out debut, and simdjson’s RVV backend experiments—from distributions and processors to the vectorization paths of specific libraries, all are advancing, and RVV is sinking from flagship projects to a routine optimization target for general-purpose libraries.
  • Embodied intelligence becomes a shared narrative for domestic RISC-V vendors: SpacemiT disclosed its “brain-cerebellum fusion chip” plans at the AI Chip Summit, and spacemit-robotics brought the RC receiver into its component system; combined with ORB-SLAM3, ros2_humanoid, and the Sophgo π0.5 port from previous issues, the RISC-V software stack in the robotics direction continues to thicken.
  • Limitations note: The data in this issue comes from public web pages and public GitHub commits, with no non-public channels used. The unauthenticated GitHub API hit its ceiling during the collection period (remaining quota reached zero), and some commit details were cross-verified via Atom feeds and the events API; the member website inspection had 70 crawl failures (mainly domestic sites and anti-scraping sites); conference-type information (Smart Car Chip Ecosystem Conference, IC WORLD Forum, AI Chip Summit) comes from multiple media outlets, with conference dates noted; Electronic Engineering Album’s “Aerospace Industry Is Gradually Adopting RISC-V as a Standard” is a recent re-publication of content from the 2026 European RISC-V Summit (original from July) and was not included as a same-day item.
  • Next issue’s focus: Whether openRuyi 2026.09 will be released; ESWIN Computing’s IPO pricing and the EIC7X release cadence; merger developments for XiangShan Kunminghu V3 and the GEM5 PDB branch; maturity progress and community response for the Tape-Out IP library; and when repositories such as DAMO XuanTie, Nuclei, and Radxa Linkr will resume pushes.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News No strongly RISC-V-related new posts within the window (renode, ipxe, etc. are routine pushes for general-purpose projects, with no RISC-V version-level developments)
Google News aggregation (multiple Chinese and English queries) English side yielded two Aheesa items, Hackaday RP2350 1080p, and a Pandaily Ruixin article (already included in the 09-21 issue, not duplicated); Chinese side yielded the ESWIN hearing, three follow-up reports on the automotive conference, openKylin, and DAMO Academy medical AI (not RISC-V, excluded); gambling and stock-market headlines were excluded wholesale on semantic grounds
Chinese industry media (Yicai / Sina Finance / Phoenix News via Wangtongshe / Science and Technology Daily / CCIDnet / Xindongxi / OSChina) Yielded the above items; EE Times China’s “Aerospace Industry Is Gradually Adopting RISC-V as a Standard” is a reprint of content from the 2026 European RISC-V Summit (original from July) and was not included as a same-day item; OSChina’s “KB Embodied Agent” is unrelated to RISC-V and was excluded
GitHub organizations and key repositories Pushes within the window: eswincomputing 3, sophgo 4, espressif 39 (spot checks showed routine WiFi / documentation / S3 Xtensa iterations, with no C-series-specific work, not listed separately), spacemit-com 4, spacemit-robotics 4, sipeed 2 (minor commits to SLogic CI and NanoKVM-Go-Apps, not listed separately), revyos 2 (routine CI and branch work, not listed separately), openRuyi-Project 5, XiangShan family 5, rt-thread/rt-thread 11 (all ARM platform and general-purpose components, falling under RT-Thread daily coverage); no pushes: XUANTIE-RV (last on 09-18), Nuclei-Software (09-04), openhwgroup, radxa-linkr (09-18)
RISC-V International official website / member websites Member website sweep of 391 companies completed (226 unchanged / 95 changed / 70 failed); all changes were homepage marketing and news-roll updates (NVIDIA, AMD, Infineon, Renesas, StarFive, etc.), with no substantive developments
openRuyi dual sources No new announcements on the official news page (latest 2026.08, 08-27); more than 20 commits in the GitHub repository within the window (already included)
CNX Software / LinuxGizmos / Phoronix RSS No new items found in two rounds of collection within this window