Research window: Past 24 hours (2026-09-22 05:00 ~ 2026-09-23 05:00, Beijing Time). Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), ITHome, Sina Tech, Kuaikeji, New Express, Ziniu News, TrendForce, More Than Moore, RISC-V International official website and blog, openRuyi official news page, RISC-V International member company website sweep (391 companies), and GitHub (XiangShan/NEMU/GEM5/difftest, XUANTIE-RV, sophgo, spacemit-com/spacemit-robotics, sipeed, revyos, riscv/meta-riscv, openRuyi-Project, Espressif, and other organizations’ and key repositories’ push and commit searches)

Index

  • Today’s Highlights: Yunqi Conference: DAMO XuanTie (T-Head) releases Zhenwu V900, first unveils Yitian 720/730/750 CPU roadmap (09-22)
  • I. Open Source Community and Software Ecosystem
    • XiangShan: master merges vector floating-point instruction support, multiple fixes in NEMU/GEM5/difftest (09-22)
    • meta-riscv: BeagleV-Fire board support merged, BeagleV-Ahead adds SD card boot (09-22)
    • Tiny-Vedas releases arxiv-v0 snapshot: RISC-V AI accelerator open-source infrastructure enters paper version (09-22)
    • Open source ecosystem shorts: RVVM floating-point unit fix, Zeitlos FPGA project progress, SLogic toolchain corrections (09-22)
  • II. Product and Ecosystem Updates
    • AI Infra Summit retrospective: Epic Semi all-RISC-V server debuts, RISC-V control cores “everywhere” (reported 09-22)
  • III. Domestic Team Deep Dive
    • DAMO XuanTie: privileged test repository damo-rv-priv-ats refactors hypervisor test suite (09-22)
    • SpacemiT: edk2-spacemit triple release 0.0.7 to 0.0.9, K3 UEFI firmware moves to Debian packages (09-22)
    • SpacemiT software stack: detection post-processing optimization, mpp stream packet reference passing and embedded model presets (09-22)
    • Sophgo: Qwen3.5 35B-A3B (MoE) adapted to CV84X6, YOLOv8-seg supports CV186X dual-core (09-22)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT spacemit-robotics: Linglong humanoid robot corrects stance and dynamics policy gains (09-22)
  • V. Summary and Trend Observations

Today’s Highlight: Yunqi Conference: DAMO XuanTie (T-Head) Unveils Zhenwu V900, First Public Roadmap for Yitian 720/730/750 CPUs

Date: 2026-09-22 (2026 Hangzhou Yunqi Conference, September 22–24)　Sources: ITHome “Alibaba T-Head Unveils CPU Roadmap for the First Time: Yitian 720, 730, 750 Three Generations of Chips Coming”, Sina Tech “Alibaba T-Head Announces CPU Roadmap”, MyDrivers “Major Progress on Alibaba T-Head’s Dual Chips: China’s Most Powerful AI Chip Zhenwu V900 Debuts, Two Generations of Yitian CPUs Slated for 2027”, TrendForce “Alibaba Unveils AI Chip Zhenwu V900 for 1Q27 Mass Production, Maps Out New Server CPUs for 3Q27”

On September 22, the 2026 Hangzhou Yunqi Conference opened. In the main forum, Alibaba Group CEO Wu Yongming positioned AI models, AI chips, and AI cloud as the three cornerstones of the “machine intelligence” era. DAMO XuanTie (T-Head) unveiled its new-generation training-and-inference-integrated AI chip, Zhenwu V900: it adopts a self-developed parallel computing architecture, carries 216GB of high-capacity memory, features 1200GB/s inter-chip interconnect bandwidth, delivers 3x the single-chip performance of the previous-generation Zhenwu M890, natively supports FP8 and FP4 low-precision computing, and targets the full spectrum of training and inference for trillion-parameter large models; Wu Yongming called it “currently China’s most powerful AI chip in terms of computing performance.” According to disclosures, the V900 will enter mass production and go on sale in Q1 2027 and be deployed at scale in Alibaba Cloud data centers; the accompanying new-generation Panjiu supernode server will launch in Q1 2027, and its self-developed ICN Switch can connect up to 500,000 V900 chips in a single cluster.

At the same event, T-Head published its Yitian server CPU roadmap for the first time: Yitian 720 and Yitian 730 will launch in Q3 2027—the 720 targets throughput- and concurrency-oriented workloads (192 cores, 96 PCIe lanes, focused on cost per core, serving the large-scale concurrent execution of Agentic Rack); the 730 is the first to be based on a fully self-developed CPU microarchitecture (the earlier Yitian 710 used Arm Neoverse IP cores), supports two-way simultaneous multithreading (SMT) and 128 PCIe lanes, and improves single-core SPECint2017/GHz by up to 1.4x over the Yitian 710, targeting latency-sensitive scenarios such as AI Head Node; the subsequent Yitian 750 will adopt a second-generation self-developed core and, for the first time, natively support the self-developed ICN interconnect protocol, enabling direct interconnection between Yitian CPUs and Zhenwu AI chips. T-Head said that with five product lines in place—Zhenwu AI chips, Yitian CPUs, ICN Switch, Panmai smart NICs, and Zhenyue storage controllers—its data center core chips have achieved full-stack self-development across “computing power, network power, and storage power.”

Boundary and background note: Neither the Zhenwu nor the Yitian series is a RISC-V product (Yitian continues to use the Arm instruction set), and this entry is included under the “domestic teams digging deeper” category—DAMO XuanTie is a core team in the RISC-V ecosystem (XuanTie C-series processor IP, the “Wujian Alliance,” and joint development of the next-generation open-source XiangShan with the Beijing Institute of Open Source Chip / Institute of Software, Chinese Academy of Sciences), and its data center self-development track advances in parallel within the same team as the RISC-V high-performance cores long tracked by this report (XuanTie C950, etc.). Separately, according to official figures (as of April 2026), the Zhenwu series has cumulatively shipped 560,000 units, serving more than 400 customers across over 20 industries, and the underlying software stack T-Head SAIL was open-sourced during WAIC in July 2026.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Vector Floating-Point Instruction Support Merged into master, Multiple Fixes in NEMU/GEM5/difftest

Date: 2026-09-22　Source: XiangShan commit: feat(vector): support vector-float instructions, XiangShan commit: decode adds Zicbop instructions (#6586), NEMU #1222

Three commits landed in the main XiangShan repository during the window. The most significant is “feat(vector): support vector-float instructions,” which adds a floating-point vector computation path to the Kunminghu vector unit and cleans up vecRegion connections accordingly; on the decode side, the missing Zicbop instructions were added to uopTable (#6586). Peripheral simulation and verification repositories received synchronized fixes: two in NEMU — unimplemented NutShell CSRs are now omitted (#1222), and CY/TM/IR remain writable when Zicntr is absent (#1223); three in GEM5 — mem-cache enables hit-under-block after fixing the probeHit boundary (#1164), cpu-o3 disables IBuffer bypass to fix pflush vset (#1135), and SMT adds a per-IQ safe watermark policy (#1175); two in difftest — iotrace preserves the last zstd block at EOF (#972), and the OpenIOMMU file list is now conditionally appended (#974). No new commits appeared in XSCache during the window.

1.2 meta-riscv: BeagleV-Fire Board Support Merged, BeagleV-Ahead Gains SD Card Boot

Date: 2026-09-22　Source: meta-riscv: beaglev-fire new MACHINE, meta-riscv: hss-payload-generator-native recipe, meta-riscv: beaglev-ahead SD card boot support

Five commits landed in meta-riscv, the Yocto RISC-V layer, during the window: a new BeagleV-Fire (Microchip PolarFire SoC) board BSP and its companion hss-payload-generator-native recipe (the HSS boot payload generation tool for PolarFire SoC); SD card boot support for BeagleV-Ahead; gptfdisk upgraded to 1.0.10; and RTOS cores disabled in the milkv-duo-fsbl small-core FSBL. With BeagleV-Fire and its boot toolchain entering the Yocto mainline layer, this open-source hardware platform — combining “FPGA fabric + 4 RISC-V cores” — now has a complete distribution build path.

1.3 Tiny-Vedas Releases arxiv-v0 Snapshot: RISC-V AI Accelerator Open-Source Infrastructure Reaches Paper Version

Date: 2026-09-22　Source: Tiny-Vedas release: arxiv-v0, Snapshot commit: arXiv v0 paper source files

Tiny-Vedas (56 stars), an open-source infrastructure project for RISC-V AI accelerators, released the arxiv-v0 snapshot during the window: the STREAM YOLO example, U280 FPGA stubs, and paper source files were frozen together, corresponding to its arXiv v0 preprint (no public entry for the paper version has yet been found on arXiv). The project provides a complete chain from a synthesizable RV32IM core (4-stage pipeline) and an 8x8 int8 GEMM accelerator (sharing DCCM via AXI4), through Python ISS/RTL co-verification, to PyTorch JIT (torch.compile to C to RV32 ELF). Its roadmap covers multiple microarchitecture extensions including VLIW, superscalar, out-of-order, and vector units, with physical design based on sv2v and OpenROAD. The project was created in April 2025; this snapshot marks its methodology reaching a citable stage. (Note: an individual-led open-source project with no tape-out record yet.)

1.4 Open-Source Ecosystem Shorts: RVVM Floating-Point Fixes, Zeitlos FPGA Project Progress, SLogic Toolchain Fixes

Date: 2026-09-22　Source: RVVM merges fcvt dynamic rounding fix (#260), Zeitlos commit: jumploader and TTS improvements, slogic16u3-tools: flash verification logic fix

Four lightweight updates: First, the RISC-V virtual machine RVVM (~1.3k stars) merged five floating-point fixes during the window — fcvt dynamic rounding modes, fcsr reserved bits and frm clarification, and NaN and sqrt result normalization (#259, #260, #280) — continuing to polish spec conformance of floating-point behavior. Second, machdyne’s RISC-V FPGA SOC/OS project Zeitlos (PicoRV32/Zeitlos32 cores, 48MHz) saw nine密集 commits — gateware support for loading from arbitrary flash locations, configurable flash writability, speech synthesis improvements, and more. Third, Sipeed’s SLogic16U3 logic analyzer toolchain fixed blank flash verification (switching to openFPGALoader readback verification instead of exit codes). Fourth, Tenstorrent’s RISC-V core verification component rv_tester added valgrind support (#70).

II. Product and Ecosystem Developments

2.1 AI Infra Summit Recap: Epic Semi’s All-RISC-V Server Debuts, RISC-V Control Cores “Everywhere”

Date: 2026-09-22 report (event 2026-09-15 to 09-17)　Source: More Than Moore “AI Infra Summit Day 2: Threads + Highlights”

More Than Moore published its Day 2 recap of the AI Infra Summit (September 15–17, Santa Clara) on 09-22 (author Dustin Sklavos, former AnandTech senior editor and Tenstorrent product manager): SiFive and Akeana booths occupied one corner of the show floor, while Epic Semi showcased a “top-to-bottom all-RISC-V” server solution at a formal booth — both the host CPU and AI processor are based on RISC-V cores. The article specifically notes that RISC-V’s presence at the show far exceeded its booth footprint: Tenstorrent’s AI architecture and CPU product lines both use RISC-V cores, Axelera uses RISC-V cores for dataflow control on its AI cards, and Xcena’s MX1 CXL memory and flash expansion module uses over a thousand RISC-V cores for data movement and caching. Combined with the SiFive and AMD ROCm porting demonstrations already covered in our 09-16 and 09-17 issues, RISC-V’s role as the “control plane/orchestration layer” in AI infrastructure is further corroborated.

III. Deep Dive into Domestic Teams

3.1 DAMO XuanTie: Privilege Test Repository damo-rv-priv-ats Refactors Hypervisor Test Suite

Date: 2026-09-22　Source: damo-rv-priv-ats commit: Test suite switched to run via PLATFORM or SUITE

One repository pushed within the DAMO XuanTie GitHub organization window: the privileged architecture test repository damo-rv-priv-ats committed a test suite refactor (enabling test suites to run via PLATFORM or SUITE configuration), continuing its main thread of “aligning tests with specifications” (PR #32 covered in the previous issue established links between test plans and specification clauses). The organization’s remaining 70-plus public repositories saw no pushes during the window—combined with the Yunqi Conference announcements (see today’s highlights), its engineering cadence is in a disclosure period for its data center chip roadmap; on the RISC-V side, it maintains momentum through testing and specification work.

3.2 SpacemiT: edk2-spacemit Triple Release 0.0.7 to 0.0.9, K3 UEFI Firmware Moves to Debian Packages

Date: 2026-09-22　Source: edk2-spacemit: release 0.0.9, edk2 and edk2-platforms converted to in-repo inline source, postinst: Spacemit K3 detection fix

The SpacemiT UEFI firmware repository edk2-spacemit pushed 20 commits in batch during the window: three consecutive releases 0.0.7, 0.0.8, and 0.0.9; conversion of edk2 and edk2-platforms from submodules to in-repo inline source synced to the latest upstream commits; and accompanying Debian packaging improvements—control dependencies, gitignore policy documentation, on-demand loading of the mtdblock kernel module in postinst, a fix for Spacemit K3 platform detection, and using the deb version number as the edk2 platform version. EDK2 is a core component of the UEFI boot chain for platforms such as K3; the shift to Debian-based packaging typically means firmware will be distributed and updated to developers and customers through the Ubuntu/Debian image ecosystem.

3.3 SpacemiT Software Stack: Detection Post-Processing Optimization, mpp Stream Packet Reference Passing, and Embedding Model Presets

Date: 2026-09-22　Source: model-zoo-vision #90: NMS and detection post-processing tightened, mpp: stream packets passed by VB reference, ai-gateway #42: Qwen3-Embedding preset

The SpacemiT software stack advanced on multiple fronts during the window: the vision model library model-zoo-vision saw two items—tightening NMS and post-processing for detection models (#90) and switching example inputs to camera default configuration (#91); mpp (multimedia processing platform) added “stream packets passed by VB (video buffer) reference,” reducing data copies in the pipeline; ai-gateway added a Qwen3-Embedding-0.6B-Q8_0 embedding model preset (#42); ai-sdk synced the vision and gateway submodules twice; the spacemit-com FlagTree branch added documentation for new builtins (#1120); and docs-ros added English documentation for K3 and Reachy voice commands. This continues its cadence of “synchronously thickening the AI and robotics software stack.”

3.4 Sophgo: Qwen3.5 35B-A3B (MoE) Ported to CV84X6, YOLOv8-seg Supports CV186X Dual-Core

Date: 2026-09-22　Source: sophon-demo: Qwen3.5 35B-A3B (MoE) ported to CV84X6, sophon-demo: YOLOv8_plus_seg supports CV186X/2core, sophon-tools #202: VPP_USAGE covers all VPSS components

Three threads within the Sophgo window: sophon-demo ported Qwen3.5 35B-A3B (MoE architecture) to the CV84X6 platform—extending the model after the previous issue’s Qwen3.5 prefix cache fix; and added CV186X dual-core support for YOLOv8_plus_seg_fuse. sophon-tools’ get_info plotting configuration expanded VPP_USAGE coverage from 5 items to all 13 VPSS components (#202), continuing to improve operational visualization for the new-generation package form factors (CV84X6/CV186X). The synchronized support for MoE large models and multi-core vision examples across its TPU product line shows that software support is still being rapidly filled in.

IV. Embodied Intelligence and Robotics Special Section

4.1 SpacemiT spacemit-robotics: Linglong Humanoid Robot Corrects Stance and Dynamics Policy Gains

Date: 2026-09-22　Source: humanoid_linglong #14: Corrected dynamics mimic policy, humanoid_linglong #15: Stance policy gain correction (merged)

The spacemit-robotics Linglong humanoid robot project merged two sets of policy corrections during the window: #14 configured a “corrected-dynamics” mimic policy, and #15 adopted the corrected stance policy gains in standing control (merged into the main branch that day). This is ongoing calibration of the deviation between policy outputs on real hardware and simulated dynamics, a routine fine-tuning step in its “simulation training to real-machine deployment” loop. The organization’s peripherals-imu and peripherals-motor saw no main-branch commits during the window (branch-level pushes were detected).

V. Summary and Trend Observations

  • The “full-stack self-development” of domestic data center chips reached new density at the Yunqi Conference: T-Head’s five product lines (Zhenwu AI chip, Yitian CPU, ICN Switch, Panmai smart NIC, Zhenyue storage controller) are in place, with Yitian 730 shifting to a fully self-developed microarchitecture. In parallel, the same team’s RISC-V line (XuanTie C series, Wujian Alliance) continues as a core asset of the open instruction set ecosystem—the pattern of “self-developed microarchitecture sprinting for data center performance” and “open instruction set expanding the ecosystem” advancing simultaneously within the same company is worth continued tracking.
  • RISC-V’s “control plane” role in AI infrastructure is reaffirmed: The AI Infra Summit retrospective shows that from Tenstorrent’s large-core matrices and Axelera’s dataflow control to Xcena MX1 using thousand-scale RISC-V cores for data movement, RISC-V is becoming “ubiquitous” as the orchestration layer of AI chips; Epic Semi’s all-RISC-V server solution provides a complete-system form factor sample.
  • “Correctness catch-up” in open-source hardware: This issue’s XiangShan vector floating-point instruction support, five RVVM floating-point fixes, and BeagleV-Fire platform completion point to RISC-V floating-point and vector correctness refinement from flagship cores down to emulators and distribution layers—precisely the most intensive type of work in the “from usable to good” stage.
  • Quiet-side observations: openRuyi saw no updates in either source (official news page and GitHub repository) during the window, and the 2026.09 release remains unpublished; Espressif’s 34 repository pushes were sampled and found to be routine USB/Bluetooth/WiFi/CI iterations with no ESP32-C series specifics; Nuclei, ESWIN, revyos, and Radxa Linkr saw no pushes during the window.
  • Limitations note: This issue’s data comes from public web pages and public GitHub commits; no non-public channels were used. Yunqi Conference information comes from multiple sources including ITHome, Sina Tech, Kuaikeji, New Express, Ziniu News, and TrendForce, and has been cross-checked; some longer-term roadmap timing differs among media outlets and was not adopted item by item; 70 member official websites failed to be crawled (mainly domestic sites and anti-scraping sites).
  • Next issue’s focus: RISC-V-related content in the Yunqi Conference agenda for 09-23 to 09-24; whether openRuyi 2026.09 is released; follow-up merge activity for XiangShan vector floating-point commits; ESWIN’s IPO process and EIC7X release cadence.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News No strongly RISC-V-related new posts within the window
Google News aggregation (multiple Chinese and English queries) English side yielded multiple pieces on the Yunqi Conference Zhenwu V900/Yitian roadmap, an AI Infra Summit recap, and multiple SEMICON India 2026 recaps (events from 09-17 to 09-19, already covered in the 09-21 issue, not duplicated); Chinese side yielded the Yunqi Conference series (Zhenwu V900, Yitian CPU roadmap) and follow-ups on ESWIN’s hearing (already covered in the 09-22 issue); gambling and sports headlines were removed in bulk by semantic filtering
Chinese industry media (ITHome/Sina Tech/MyDrivers/New Express/Ziniu News/EE Times China) Yunqi Conference items found, cross-checked and consistent across multiple sources; no new content directly related to RISC-V identified
GitHub organizations and key repositories Pushes within the window: XUANTIE-RV 1, eswincomputing 0, sophgo 3, Nuclei-Software 0, espressif 34 (spot-checked as routine USB/Bluetooth/WiFi/CI iterations, no C-series-specific work), spacemit-com 9, spacemit-robotics 3, sipeed 3, revyos 0, openhwgroup 0, radxa-linkr 0, openRuyi-Project 0, XiangShan family 5
RISC-V International official website/blog Latest blog post remains 09-17 (Openchip interview), no new articles within the window; member website sweep of 391 companies completed (228 unchanged/93 changed/70 failed), all changes were homepage marketing and news ticker updates with no substantive developments
openRuyi dual sources No new announcements on the official news page (none published in 2026.09, latest is 2026.08); no pushes to the GitHub repository within the window
CNX Software/LinuxGizmos/Phoronix RSS No new items within the window