Research window: Past 24 hours (2026-09-23 05:00 ~ 2026-09-24 05:00, Beijing time). Sources: Hacker News, Google News aggregation (multiple Chinese and English queries, via proxy), Gasgoo, PEdaily, JiWei.com, MyDrivers, Beijing Daily, Sina Finance, RISC-V International official website and blog, openRuyi official news page, RISC-V International member company website sweep (391 companies), and GitHub (XiangShan/NEMU/GEM5/difftest/XSCache, openRuyi-Project, DAMO XuanTie XUANTIE-RV, ESWIN Computing, Sophgo, SpacemiT spacemit-com/spacemit-robotics, Sipeed, revyos, riscv/meta-riscv, Espressif, and other organizations’ and key repositories’ push and commit searches)

Index

  • Today’s Highlight: riscv.org blog publishes Monte Cimone v3: Third-generation evaluation of SOPHGO SG2044-based RISC-V HPC testbed completed (09-23)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan: XSCache “Oceanus” L2 cache parallel development advances, multiple fixes for Kunminghu v3 and vector branches (09-23)
    • openRuyi-Project: kvm-unit-tests adds BRS SBI requirement tests, toolchain and desktop documentation advance across multiple repos (09-23)
    • Open-source ecosystem briefs: meta-riscv, felix86, SLogic toolchain and qtrvsim fixes (09-23)
  • II. Product and Ecosystem Developments
    • Gasgoo publishes final installment of RISC-V automotive chip trilogy: “What Comes After Getting On Board” (09-23)
    • Ruixin Gaoguang D35 debuts at the 5th Global Digital Trade Expo, multiple reports focus on dataflow architecture and robotics scenarios (09-23)
  • III. Deep Dive into Domestic Teams
    • Aowei Lingxin: Completes over RMB 200 million Pre-A+ round, Pre-A series totals over RMB 300 million (09-23)
    • SOPHGO: LLM-TPU adds multi-image input and ViT output caching for Qwen3.5 demo (09-23)
    • SpacemiT: spine-runtime v0.6.3 released, software stack and documentation infrastructure updated at multiple points (09-23)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT spacemit-robotics: Humanoid robot adds RGB-D SLAM and Nav2 support, motor driver and perception modules updated (09-23)
  • V. Summary and Trend Observations

Today’s Highlight: riscv.org Blog Publishes Monte Cimone v3: Third-Generation Evaluation of SOPHGO SG2044-Based RISC-V HPC Testbed Completed

Date: 2026-09-23　Source: RISC-V International Blog “Monte Cimone v3: Where RISC-V Stands in High-Performance Computing”

On September 23, the RISC-V International official blog published the Monte Cimone v3 (MCv3) evaluation jointly completed by the University of Bologna, Italy’s Cineca supercomputing center, and E4 Computer Engineering: the third generation of this RISC-V HPC testbed builds a cluster based on SOPHGO Sophon SG2044 processors, uses HPL and STREAM benchmarks with simultaneous power measurement, and benchmarks against Intel Xeon Platinum 8480+ (Sapphire Rapids) and NVIDIA Grace CPU Superchip platforms. Key data from the article: SG2044 single-core performance more than doubles compared to the previous generation SG2042, with cluster scalability improving in tandem; MCv3 achieves energy efficiency of 3.08 GFLOPs/W (approximately 10x that of the first-generation MCv1), and at the peak efficiency point reaches 46% of Sapphire Rapids and 91% of Grace CPU Superchip performance. The author team includes Luca Benini, Andrea Bartolini, and other scholars from the University of Bologna long engaged in energy-efficient computing research; MCv3 also continues the testbed’s positioning of “quantitative evaluation for real HPC workloads.”

Significance and boundaries: This is the first time a third-party academic team has placed a domestic RISC-V server chip (SG2044) into the same benchmarking framework as Intel and NVIDIA server platforms to provide energy-efficiency point comparisons. The RISC-V HPC narrative has upgraded from “can run” to “possesses a comparable energy-efficiency advantage zone.” At the same time, note the comparison basis — total performance still lags (46%), and the comparison primarily observes energy-efficiency points (peak efficiency), indicating that the realistic entry point for RISC-V servers remains energy-sensitive and open-customizable scenarios, rather than full performance replacement. SG2044 was released by SOPHGO in 2025 (64 cores, entering multiple HPC test environments during the same period), and this evaluation provides another quantitative endorsement through public academic channels.

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: XSCache “Oceanus” L2 Cache Parallel Development Advances, Multiple Fixes in Kunminghu v3 and Vector Branches

Date: 2026-09-23　Source: XSCache commit: L2 port parameterization (09-23), XSCache commit: StashShared/StashUnique support (09-23), XSCache commit: Oceanus L2 exposes AMBA CHI port (09-23), XiangShan commit: #6590 (09-23), NEMU release v2026.09.r17 (09-23)

The “Oceanus” next-generation L2 development branch of XiangShan’s cache subsystem XSCache advanced 20 commits during the window, the densest open-source development stream of the day: centered on L2 parameterization (configurable port count, compatible with multiple D-Cache bank combinations), AMBA CHI bus port exposure (TestTop exposing a CHI interface externally, evolving toward multi-core/coherent interconnect), and CHI-semantics StashShared/StashUnique transaction support; alongside fixes for serialization of EVT commits and peer metadata writes, bypassing EvictBack when ReplRd returns I state, and overly strict client update assertions, among other coherence issues. The main repository’s Kunminghu v3 branch fixed a pingpong deadlock on cross-16B-aligned loads/stores (#6590); the vector development branch (0923) continued polishing the vector memory access path with 7 commits—vector store mask support, VL dependency tracking, vle exception handling, vldSNMergeInfo initial value correction, etc.—continuing the fix cadence after the 09-22 issue’s “vector floating-point instruction support merged.” On the simulation and verification side: NEMU released v2026.09.r17; GEM5 saw three items (FP division latency cross-format alignment #1167, KMHV3 vector computation issue queue alignment #1179); difftest fixed an AME MinimalMatrixConfig validator compatibility issue.

1.2 openRuyi-Project: kvm-unit-tests Adds BRS SBI Requirement Tests, Toolchain and Desktop Docs Advance Across Multiple Repos

Date: 2026-09-23　Source: kvm-unit-tests commit: BRS SBI requirement tests (09-23), kvm-unit-tests commit: decouple SBI console from UART initialization (09-23), openRuyi commit: vkmark patch backport (09-23), openRuyi-Project/homepage commit: desktop user documentation (09-23)

Six repositories were active during the window in the openRuyi project led by the Institute of Software, Chinese Academy of Sciences. Most notable is the addition of BRS (Boot and Runtime Services) SBI requirement tests on the RISC-V side of kvm-unit-tests: BRS is the next-generation specification for the RISC-V boot flow, and this commit adds a testing hook for distributions to verify “BRS-compliant firmware/boot chains,” while decoupling SBI console initialization from UART (to facilitate running tests in environments without a traditional serial port). The main distribution repository continued SPECS maintenance: backporting a patch fixing vkmark crashes on lavapipe software Vulkan, and introducing SPDX header checks; on the toolchain side, clang-wrap regularized linker options and static library member selection, and llvmir-converter preserved protected target features and cached versioned native templates; the homepage repository added openRuyi desktop user documentation; ceph-ci adjusted the build concurrency limit. No new announcements appeared on the homepage news page during this window (the 2026.09 release has not yet shipped).

1.3 Open-Source Ecosystem Shorts: meta-riscv, felix86, SLogic Toolchain, and qtrvsim Fixes

Date: 2026-09-23　Source: meta-riscv commit (09-23), felix86 commit: update RIP after x87 operations (#784), felix86 commit: signal race before futex locking (#787), libsigrok commit: SLogic zero-progress capture recovery (09-23), slogic16u3-tools v0.1.3 release (09-23)

  • Yocto’s RISC-V layer meta-riscv added a “usage restrictions” note for BeagleV-Fire (documentation wrap-up following the board BSP inclusion in the 09-22 issue).
  • The binary translation project felix86, which runs x86/x86-64 programs on RISC-V Linux, saw 5 commits during the window: fixing RIP updates after x87 operations and a signal race before futex locking, implementing the VK_AMD_buffer_marker graphics thunk, and optimizing MSVC string lookup—continuing to advance gaming-scenario compatibility.
  • Sipeed’s SLogic logic analyzer toolchain: the libsigrok driver fixed a “zero-progress capture” stall (recoverable after an exception), and slogic16u3-tools released v0.1.3 (more detailed flashing verification logs, self-explanatory on failure).
  • The educational RISC-V simulator qtrvsim fixed window size and modal event loop issues in the WebAssembly build (5 commits).

II. Product and Ecosystem Updates

2.1 Gasgoo Publishes Final Installment of Its RISC-V Automotive Chip Trilogy: “After Entering Vehicles, What Does It Compete On?”

Date: 2026-09-23　Source: Gasgoo, “RISC-V, After Entering Vehicles, What Does It Compete On?”

Gasgoo’s English site published on 09-23 the third article in its RISC-V automotive chip series (the first two covered “why it suddenly heated up” and “how to overcome fragmentation”; this is the final installment). Key points: volume production footholds have already emerged in edge scenarios such as body control — the M100 from Zijin Semiconductor, incubated by Great Wall Motor’s Technology Center, is used in body control for combination headlights, ambient lighting, and switches; Dongfeng’s DF30 has completed multi-model validation and is planned for volume production in 2026 (already covered in the 09-21/09-22 issues); industry sources say that since August 2024, multiple domestic RISC-V automotive-grade MCUs have entered volume production, with another batch expected in 2026; large chips for intelligent driving and cockpits currently still appear in the form of auxiliary cores/dedicated acceleration units (Horizon Journey 6 partially uses RISC-V cores, Mobileye EyeQ Ultra), while the main control CPU remains Arm/x86. The cost equation: Arm core licensing fees run from several million to over ten million yuan depending on tier, plus royalties after volume production, whereas commercial RISC-V core licensing fees are about one-tenth of that — but “free” refers only to the instruction set layer; commercial IP, tools, and verification environments all require payment, and ecosystem investment is the main barrier (Infineon invested in the ecosystem 2 to 3 years ahead; DAMO Academy’s Li Weili says full automotive-grade certification takes 3 to 5 years). Ecosystem and pace: the Quintauris alliance (initiated by Bosch, Infineon, NXP, Qualcomm, and others) has begun cooperation with Nuclei; penetration is expected to rise from about 10% in 2025-2026 to about 31% by 2031; the development path is “edge to center” (body/powertrain control first, then entering via general-purpose/control cores in large chips); the conclusion is short-term complementarity with Arm and long-term coexistence. This is media industry analysis (not a brand-new event); this issue summarizes its key points to complete tracking of the series.

2.2 Ruixin Gaoguang D35 Debuts at the 5th Global Digital Trade Expo, with Multiple Reports Focusing on Dataflow Architecture and Robotics Scenarios

Date: 2026-09-23　Source: Drivers’ Home, “On Site: The Most ‘Hardcore’ Booth at the Digital Trade Expo: One Dataflow Chip Powers Five Major AI Scenarios” (09-23), Beijing Daily Online, “The 5th Global Digital Trade Expo Opens Today: Fully Self-Developed Physical AI Chip Makes Full-Scenario Debut in Hangzhou” (09-23), Sina Finance, “World’s First RISC-V Dataflow Physical Chip in Mass Production: 12nm Performance Beats Nvidia 7nm” (09-23), Jiwei, “Dataflow Architecture Enters Embodied Intelligence: Why Gaoguang D35 Became Qiyuan Robotics’ Compute Partner” (09-23)

The 5th Global Digital Trade Expo opened in Hangzhou on 09-23, where Suzhou Ruixin’s Gaoguang D35 dataflow chip was exhibited on site as a “fully self-developed physical AI chip” (Drivers’ Home called it the expo’s most “hardcore” booth, able to “power five major AI scenarios”); Jiwei published an article the same day analyzing the architectural reasons why D35 became Qiyuan Robotics’ compute partner (triggering computation on data arrival, reducing data movement overhead); Sina Finance and others reported its mass production under the headline “12nm performance beats Nvidia 7nm” (media/vendor promotional framing). This item is a continuation of the 09-21 issue’s “Gaoguang D35 enters mass production and joins the Qiyuan Robotics ecosystem” at the level of exhibition display and follow-up coverage; for information on the mass-production entity, see the earlier report, and it is not repeated here.

III. Deep Dive into Domestic Teams

3.1 Aowei Lingxin: Completes Over RMB 200 Million Pre-A+ Round, Pre-A Series Totals Over RMB 300 Million

Date: 2026-09-23　Source: Pedaily “Aowei Lingxin Completes Over RMB 200 Million Pre-A+ Round, Focused on High-Performance RISC-V Processor Development” (09-23)

Shenzhen Aowei Lingxin Technology Co., Ltd. announced on 09-23 that it completed full capital settlement of its Pre-A+ round this month, amounting to over RMB 200 million: this round introduced state-owned-backed institutions including Suzhou Venture Capital, Guoxin Guozheng, Puhua SME Phase II, and Chengdu Peikun, as well as industrial capital including SigmaStar, Juhe Capital, Shenzhen Industrial Investment, and Amara Yuehai, with participation from well-known investor Wei Wei, and continued follow-on investment from existing shareholders; the Pre-A round was previously led by the Chuangdongfang Fund under Longgang Financial Holdings. With this, the Pre-A and Pre-A+ rounds together total over RMB 300 million, with funds to be invested in next-generation chip R&D, team expansion, and commercialization (network communications, edge computing, distributed storage, AI inference). The technical path is a “RISC-V foundation + DSA modular configurable heterogeneous architecture” (capable of integrating near-memory computing units on demand to alleviate data throughput bottlenecks), and its self-developed RV9000 series has completed tape-out and lit up (up to 24 heterogeneous compute cores, with a built-in national cryptographic security engine and high-speed I/O).

Deep dive and background: The company completed RV9000 tape-out and lit up on 09-15 (covered in the 09-16 issue); this financing means it has moved from a “R&D milestone” into a “scaled R&D + commercialization introduction” phase; among the investors, SigmaStar (a security SoC vendor) participates as industrial capital, pointing to synergy potential in edge computing and vision scenarios; Shenzhen state capital (the Longgang Financial Holdings system) has repeatedly increased its stake, continuing Shenzhen’s track record of policy support for RISC-V chips. Boundaries: The financing amount, investors, and use of funds are all cited from the company’s official announcement; the chip still has no third-party performance data or mass-production timeline.

3.2 SOPHGO: LLM-TPU Adds Multi-Image Input and ViT Output Caching to Qwen3.5 Demos

Date: 2026-09-23　Source: LLM-TPU commit (09-23)

SOPHGO’s large-model deployment repository LLM-TPU committed within the window “feat: add multi-image input and ViT output caching to Qwen3.5 demos”: adding multi-image input support and ViT output caching (reducing repeated computation in the vision encoder) to the Qwen3.5 series demos, continuing its push toward multimodal capabilities after “supporting text-only Qwen3.5” in the 09-15 issue. On the same day, the Monte Cimone v3 HPC benchmark published on the riscv.org blog (see today’s highlights) used precisely the SOPHGO Sophon SG2044 processor—SOPHGO’s ecosystem moves are visible simultaneously across two product lines: “cloud-side TPU inference” and “RISC-V server CPU.”

3.3 SpacemiT: spine-runtime v0.6.3 Released, Multiple Updates Across Software Stack and Documentation Infrastructure

Date: 2026-09-23　Source: spine-runtime v0.6.3 release (09-23), model-zoo-vision #92 commit (09-23), mpp commit: vdec channel lifecycle simplification (09-23), ai-sdk commit (09-23)

SpacemiT had pushes across 7 repositories within the window: spine-runtime released v0.6.3 (an AI multi-core execution runtime for its RISC-V SoCs, responsible for task scheduling and synchronization between general-purpose cores and AI compute cores); model-zoo-vision added benchmark scenarios and clearer inference timing (#92); mpp multimedia middleware had three fixes (vdec channel lifecycle simplification, MJPEG MP4 sampling buffer expansion, test assets switched to downloading from Nexus); ai-sdk updated vision submodule pointers; docs-chip and docs-product integrated terminology/description lint and knowledge synchronization processes (documentation infrastructure). These are continuous iterations of the K3 platform software stack and toolchain, with no version-level major release.

IV. Embodied Intelligence and Robotics Special Chapter

4.1 SpacemiT spacemit-robotics: Humanoid Robot Adds RGB-D SLAM and Nav2 Support, Motor Drive and Perception Modules Updated

Date: 2026-09-23　Source: ros2_humanoid commit (09-23), peripherals-motor commit (09-23), perception commit (09-23)

SpacemiT’s robotics line (spacemit-robotics) had pushes across 4 repositories within the window: ros2_humanoid added RGB-D SLAM and Nav2 navigation support—its humanoid robot ROS 2 stack (which previously provided a bridge node for Nav2 velocity commands into the RL motion control chain and head TF publishing) continues advancing from “motion control” toward a “perception—localization—navigation” closed loop; peripherals-motor added an RS485 shared library driver for the M8010-A motor (filling in support for a new actuator model); the perception library fixed plane stitching rendering target to a fixed 1080p and updated usage documentation; the IMU peripheral repository was maintained in sync. Combined with “Linglong humanoid robot posture and dynamics policy corrections” in the 09-22 issue, SpacemiT has continuously strengthened its humanoid robot software stack (control, perception, navigation, peripheral drivers) over the past two days.

V. Summary and Trend Observations

  • HPC side gains third-party quantitative coordinates: Monte Cimone v3 benchmarks SOPHGO SG2044 against Intel Xeon and NVIDIA Grace, providing comparative data of “peak energy-efficiency points at 91% of Grace / 46% of Sapphire Rapids, 3.08 GFLOPs/W”—the RISC-V HPC narrative has upgraded from “can run” to “has a comparable energy-efficiency advantage range”; the total performance gap remains, and the realistic entry point is still energy-efficiency-sensitive and open-customizable scenarios.
  • Automotive RISC-V enters the “mass production and ecosystem investment” phase: Gasgoo’s final installment shifts the discussion from standards to delivery—body control has already landed at scale, while powertrain and intelligent driving advance along “edge to center”; the real threshold is ecosystem investment beyond licensing fees (toolchains, certification, alliance cooperation), with a penetration rate coordinate of 10% to 31% (by 2031) and a 2026 to 2030 window.
  • Capital-side enthusiasm remains undiminished: Aowei Lingxin’s over RMB 200 million Pre-A+ closes (a combination of Shenzhen state capital + industrial capital), stacking on top of Yixing Intelligent’s nearly RMB 2 billion financing and ESWIN’s hearing, the “R&D—tape-out—capital” cycle in the RISC-V processor track continues to operate domestically; the next key variable remains product delivery and order fulfillment.
  • Open-source infrastructure enters an intensive polishing period: XiangShan cache subsystem “Oceanus” and vector path parallel fixes, openRuyi adding tests for the BRS boot specification, SLogic/felix86 and other toolchain updates—all are paving actions oriented toward the next stage of productization; the openRuyi official website 2026.09 release remains a near-term observation point.
  • Embodied intelligence software stack continuously strengthened: SpacemiT’s humanoid robot fills in SLAM and navigation capabilities, echoing Suzhou Ruixin’s dataflow architecture bound to robotics scenarios, with the “edge compute + robotics software stack” combination continuing to take shape.

Limitations note: This issue’s international news side is mainly riscv.org blog and industry analysis articles, while Chinese media are mostly follow-up reports of already-covered events (Ruixin at the Digital Trade Fair, ESWIN hearing English reprints, etc.); the 92 member website inspections showed changes all at the marketing layer; the ESWIN Computing repository has push timestamps but no new commits within the window on any branch or tag (see the source verification table for details); expressions such as “12nm surpasses NVIDIA 7nm” are media headline framing and have not been verified by third-party testing.

Appendix: Complete Source List

Source Verification Table

Source Verification Result
Hacker News No strongly RISC-V-related new posts within the window
Google News aggregation (multiple Chinese and English queries) English side: Gasgoo automotive chip analysis (included in 2.1), ESWIN hearing English follow-up and SEMICON India wrap-up coverage (both events already included in the 09-21/09-22 issues, not duplicated), Aheesa Vihaan-I reposts (already included in the 09-21 issue); Chinese side: Aowei Lingxin funding (included in 3.1), Ruixin Digital Trade Expo series (included in 2.2), ESWIN hearing Chinese reprints (already included); gambling and sports headlines removed in bulk by semantic filtering
Chinese industry media (Gasgoo, PEdaily, JiWei, MyDrivers, Beijing Daily, Sina Finance) Aowei Lingxin Pre-A+ funding (verified against the original PEdaily article), Ruixin Digital Trade Expo and robotics scenario series, final installment of automotive RISC-V analysis; no other new substantive RISC-V events found
GitHub organizations and key repositories Pushes within the window: XUANTIE-RV 0, eswincomputing 2 (u-boot/linux-stable have push timestamps, but no new commits within the window on main, release, development branches, or tags, treated as no substantive code updates), sophgo 1, Nuclei-Software 0, espressif 42 (spot-checked as routine Bluetooth/WiFi/thread and engineering system iterations, no ESP32-C series specifics), spacemit-com 7, spacemit-robotics 4, sipeed 3, revyos 0, openhwgroup 1 (.github organization configuration), radxa-linkr 0, openRuyi-Project 6, XiangShan family 5 (XiangShan/NEMU/GEM5/difftest/XSCache)
RISC-V International website/blog Website blog published Monte Cimone v3 on 09-23 (included in today’s highlights); member website sweep of 391 companies completed (230 unchanged/92 changed/69 failed), all changes were homepage marketing and news ticker updates with no substantive developments
openRuyi dual-source No new announcements on the official news page (2026.09 release not yet published); 6 GitHub repositories active within the window (included in 1.2)
CNX Software/LinuxGizmos/Phoronix RSS No new entries within the window