Research window: 2026-10-30 05:00 ~ 2026-11-02 05:00 (Beijing time, 72 hours, covering the weekend).

Sources: Google News aggregation (27 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, LWN, the official riscv.org blog, the openRuyi official news page and main repository, website checks of RISC-V International member companies (391 companies), the riscv100.top leaderboard, and commit and release searches across GitHub organizations and key repositories including XiangShan/NEMU/difftest/XSCache/GEM5, CORE-V CVW/CVA6, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, and Radxa Linkr.

This Issue’s Index

  • Today’s Focus: Linux 7.4 turns “fast unaligned access” into a runtime probe, letting distribution kernels reap up to 11% bandwidth gains (10-30)
  • RISC-V 100 Leaderboard Updates
    • Leaderboard adds a 10-17 record: XSCC 2.0 on XiangShan KMHv3 RTL 3GHz, int 68.41, fp 76.95 (11-02 inspection)
    • Two old records drop off: LLVM 22.1.0 on SpacemiT K3 X100, XSCC 1.1 on Zhihe A210 C908 (11-02 inspection)
  • I. Open-Source Community and Software Ecosystem
    • XiangShan frontend introduces FtqPrefetchQueue, first step in iprefetch refactor (10-30)
    • XiangShan fixes MBTB allocation suppression for hidden VBTB branches (10-30)
    • XiangShan decodes prefetch.i/r/w into LSU prefetch operations (10-30)
    • XiangShan CI performance pipeline enables lightSSS, GEM5 weekly tests switch to 261013 config (10-30)
    • difftest: nine commits in two days; MMA backend packs FP8 products into cache words (10-30 to 11-01)
    • NEMU adds replay state rollback for AME, fixes hosttlb matrix register selector (10-30, 10-31)
    • XSCache fixes another CoupledL2 hint path being persistently blocked (10-30)
    • openRuyi introduces llvm23 23.1.4, riscv64-openruyi-linux defaults to RVA23U64 (10-30)
    • CORE-V CVW no longer caches invalid PTEs per Svvptc (10-30)
    • CORE-V CVW fixes trace VM fields and quad overflow detection, rv64gc coverage reaches 100% (10-30)
  • II. Product and Ecosystem Updates
    • Qwenputer compiles RV32IM into Qwen3.5-4B weights, uses attention state as RAM (10-30)
    • SpacemiT creates Bianbu AgentOS umbrella repo, edge agent stack locked by submodule (10-30)
    • SpacemiT docs-chip removes P1S docs, docs-product updates K3 Pico resource links (10-30)
    • Radxa Linkr adds OBS browser capture guide, initializes linkr-now-skill (10-30)
  • III. Deep Dive on Domestic Teams
    • Nuclei releases Nuclei Studio VS Code IDE preview, tool guide synced to 2026.10 (10-30)
    • Sophgo LLM-TPU supports InternVL3/LLaMa3, fixes Qwen3-ASR decoding degradation (10-30)
    • DAMO XuanTie and ESWIN: no new organization-level development in window (11-02)
  • IV. Embodied Intelligence and Robotics Special Section
    • SpacemiT adds unified robotic arm control framework, 85 files cover calibration/diagnostics/kinematics (10-30)
    • SpacemiT dice_arena adds integrated dice game application (10-30)
    • SpacemiT docs-ros adds English RealSense guide, aligns Chinese and English docs (10-30)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Source Verification Table

Today’s Focus: Linux 7.4 turns “fast unaligned access” into a runtime probe, letting distribution kernels reap up to 11% bandwidth gains (10-30)

The RISC-V architecture changes for Linux 7.4 have been merged into mainline, and one optimization deserves a separate note: the decision to skip software alignment has moved from compile time to runtime.

This optimization came about in two steps. The change submitted by Tenstorrent for Linux 7.3 let “kernels compiled for RISC-V hardware that supports fast unaligned memory copies” skip software alignment, with Tenstorrent’s own testing showing bandwidth gains of up to 11%. But 7.3 required this capability to be enabled at compile time, and a distribution kernel must serve a range of hardware, among which there are always chips with slow unaligned access—so this gain could only remain in custom kernels, out of reach for generic builds. 7.4 moves the decision onto HAVE_EFFICIENT_UNALIGNED_ACCESS as a runtime probe: only when the hardware is detected to genuinely support fast unaligned access do userspace copies skip software alignment. This way, distribution RISC-V kernels and other generic builds can carry this optimization by default, without having to keep a special image for older hardware.

Other RISC-V changes merged into 7.4 in the same batch include: crash hotplug support, some page table functions taking optimized paths, an optimization in context switching, the “B” extension entering hwcap and hwprobe reporting, and reporting support for the Zic64b extension. Individually none of these is large, but together they represent a step toward “the kernel figuring out RISC-V platform capabilities and handing them to its own scheduler”—especially the hwprobe-side reporting, which is precisely the prerequisite for optimizations like runtime probing.

One judgment from community discussion is worth recording: a reader on Hacker News asked whether fast unaligned access is exclusive to server CPUs, and a reply pointed out that nearly every vendor supports it except SiFive, which supports it only on its newer-generation performance cores. This suggests that once distributions enable this optimization, the actual benefit depends on whether chips report it truthfully in hwprobe, not on product positioning.

Date: 2026-10-30　Sources: Phoronix: RISC-V Has A Nice Portable Performance Optimization With Linux 7.4, Hacker News discussion

RISC-V 100 Leaderboard Updates

This inspection (spanning the weekend, four days after the previous 10-28 inspection) found substantive changes to the leaderboard, placed near the top of the main text per user preference.

New leaderboard entries (one each in Cross-Arch · SPEC CPU2006 and the RISC-V channel · SPEC CPU2006): 10-17 XiangShan compiler team (XSCC) XSCC 2.0 on XiangShan KMHv3 RTL 3GHz int 68.41, fp 76.95 (speed/ref, Completed); versus the previous record from the same compiler (10-15, XSCC 2.0), int +0.8%, fp +0.5%. This record is dated 10-17, earlier than this inspection date, so it is a backfilled entry—at the 10-28 inspection, the top of both CPU2006 boards was still the 10-15 int 67.85, fp 76.54.

Two entries dropped: the 07-27 record “LLVM 22.1.0 on SpacemiT K3 X100 2.4GHz” in Cross-Arch · SPEC CPU2006 dropped off; the 08-05 record “XSCC 1.1 on Zhihe A210 C908 1.9GHz” in the RISC-V channel · SPEC CPU2006 dropped off. Two removals coinciding with one backfilled entry looks more like leaderboard housekeeping than new measurements—the +0.8%/+0.5% difference under the same compiler is also within noise, and should not be read on its own as an architectural improvement.

Date: 2026-11-02　Sources: riscv100.top Cross-Arch SPEC CPU2006 board, riscv100.top RISC-V Channel SPEC CPU2006 board

I. Open-Source Community and Software Ecosystem

XiangShan frontend introduces FtqPrefetchQueue, first step in iprefetch refactor (10-30)

PR #6691 is the heaviest change to the XiangShan frontend this round: 16 files, +471/−198. The core of the change is the addition of FtqPrefetchQueue, which moves instruction-fetch prefetching up from ICache-top to the FTQ side for unified scheduling.

The three problems with the original design are stated plainly. First, the FTQ only handles FDIP; Zicbop software prefetches prefetch.i coming from memblock are handled by ICache-top, which can only accept 1 request per cycle and always ranks software prefetches at high priority—when multiple prefetch.i arrive in the same cycle, only 1 takes effect and the rest are silently dropped, yielding less performance gain than expected. Second, dense prefetch.i blocks FDIP requests, which in turn lowers performance. Third, prefetchPipe either handles 1 prefetch.i or 1 to 2 FDIPs; even when the two do not conflict on SRAM, they cannot proceed in parallel, so pipeline utilization is low.

The new queue works as follows: first buffer software prefetch requests to mitigate drops; then select the dequeue source based on queue vacancies and distance to the current FDIP to resolve blocking; and allow FDIP and prefetch to issue in parallel in the same cycle to resolve utilization. The author also left an extension point—results from PDIP-style algorithms can later be fed directly into the same queue. This is a change that turns prefetching from “a single path” into “a schedulable first-level resource,” which is closer to a long-term solution than simply adjusting priorities.

Date: 2026-10-30　Source: XiangShan #6691

XiangShan fixes MBTB allocation suppression for hidden VBTB branches (10-30)

PR #6750 fixes predictor metadata suppressing one another. During prediction, VBTB exposes only the earliest-matching branch, but during training it may still hit a “hidden branch”—one not seen at prediction time, yet whose training hit suppresses MBTB allocation, so the same branch repeatedly mispredicts.

The fix has three parts: suppress MBTB writes due to VBTB residency only when both conditions hold—the branch was actually exposed at prediction time and is still resident at training time; pass all NumWay+1 metadata entries to AlignBank so that “VBTB prediction hit” can be distinguished from “SRAM hit”; and write the conditional-branch payload only when actually taken, because the not-taken resolution path carries the sequential next PC rather than the branch target. The last point applies to both MBTB and VBTB, while counter training and IFU invalidation requests (attribute=None) are preserved. The change touches only 2 files, +33/−19, but is a typical fix of the kind where “the more complex the predictor, the more the metadata definitions must be aligned.”

Date: 2026-10-30　Source: XiangShan #6750

XiangShan decodes prefetch.i/r/w as LSU prefetch operations (10-30)

PR #6735 changes the handling flow for software prefetch instructions: prefetch.i, prefetch.r, and prefetch.w are recognized at decode as LSU prefetch operations and excluded from CROB. This step pairs with the queueing change in #6691—only by first separating prefetches from “ordinary memory-access instructions” can the FTQ-side prefetch queue have an independent request source and no longer contend with load/store for the same commit path.

Date: 2026-10-30　Source: XiangShan #6735

XiangShan CI performance flow enables lightSSS, GEM5 weekly tests switch to 261013 config (10-30)

PR #6802 upgrades the difftest version in the gsim flow and has CI enable lightSSS, so benchmarking and verification share the same snapshot mechanism and duplicate builds are avoided. In the same window, OpenXiangShan/GEM5 PR #1274 switches the weekly XSCC tests to the 261013 config profile. Both are infrastructure maintenance: the former determines “whether errors can be quickly replayed,” the latter determines “which compiler and workload combination the weekly tests run,” and neither changes RTL behavior.

Date: 2026-10-30　Source: XiangShan #6802, GEM5 #1274

difftest: nine PRs in two days—MMA backend packs FP8 products into cache words (10-30 to 11-01)

difftest submitted 9 PRs over three days, all centered on MMA (matrix multiply-accumulate) verification performance—a concentrated push in terms of cadence.

The most technical is PR #1023: adjacent FP8 product records are packed into the low 16 bits and high 16 bits of the same cache word, halving register usage; each word is first initialized with even lanes, and before decoding the two half-words are masked separately to ensure adjacent sign fields do not interfere with each other, with odd-length tail blocks handled the same way. PR #1021 moves comparison onto the GPU (11 files, +420/−90): DUT snapshot upload is decoupled from reference computation, active result rows are compared directly on the GPU, only a status byte is returned on success, and reference results are downloaded for diagnosis only on mismatch; the fallback path uses memcpy instead of the slower SSE2 streaming-store; contiguous hot slots are reused and their ranges uploaded directly from the CUDA service; and per-prefix ready/enqueue acknowledgments are removed while preserving the LightSSS session lifecycle. PR #1018 pipelines CUDA transfer, computation, and result checking; PR #1017 adds CUDA backend support to LightSSS; PR #1020 packs XDMA relay requests to reduce latency; PR #1019 simplifies signed INT8 reference reduction; PR #1016 reuses contiguous active prefixes of operand slots; and PR #1004 isolates Delta and AXI timing. The direction is clear: the verifier must no longer just “compute correctly” but also “compute affordably.”

Date: 2026-10-30 to 2026-11-01　Source: difftest commit history, #1023, #1021

NEMU adds replay state rollback for AME, fixes hosttlb matrix register selector (10-30, 10-31)

PR #1255 adds replay_state.c (178 lines), using the replay state API to snapshot and restore matrix registers, token counters, AMU control, and synchronization events; when AME_MEM_ACCESS_CHECK is enabled it also tracks matrix and scalar/vector stores, and when AME_TILEREG_UB_CHECK is enabled it tracks the tile register definition area. The snapshot is deliberately kept independent of the matrix store commit queue to avoid being polluted by uncommitted writes during rollback. PR #1274 fixes a functional bug caused by a signature mismatch: the matrix read/write definition and its callers use char m_name, but the public header declares bool isacc, so calls made through the header coerce the A/B/C selectors to true; both declarations are corrected, and a common header is introduced in host-tlb.c so that any future signature mismatch fails compilation directly.

Date: 2026-10-30, 2026-10-31　Source: NEMU #1255, NEMU #1274

XSCache fixes CoupledL2 where one hint path is continuously blocked (10-30)

PR #48 changes only one line: in CoupledL2, prevent one hint path from being continuously blocked by another. The previous day’s PR #46 had already changed hint arbitration from fixed priority to round-robin, and this is the wrap-up of the same line of work. Starvation-type problems in the cache hierarchy usually only surface under long stress tests, and behind a one-line change is a hard-to-reproduce verification effort.

Date: 2026-10-30　Source: XSCache #48

openRuyi introduces llvm23 23.1.4, riscv64-openruyi-linux defaults to RVA23U64 (10-30)

The most important of the six commits is the new llvm23 package (a 1220-line spec plus two patches). What the patches do is more informative than the version number: they add an openruyi vendor to LLVM and set the default ISA level of the riscv64-openruyi-linux triple directly to RVA23U64—that is, without passing an extra -march, the compiler generates code for RVA23. For a distribution this is a clear statement: RVA23 is no longer an “optional optimization tier” but the default baseline; the patches also wire the openruyi-linux triple into both the x86_64 and riscv64 Triple handling paths to ensure cross-builds work.

The other five are rolling maintenance: ollama upgraded to 0.40.7 and marked security-fixes; clang-wrap updated to 20261030; and two new Go language binding packages for tree-sitter, for C++ and Go, plus the go-pointer dependency. The latest item on the official news page is still the 2026.09 release (published 9-30); the October release has not yet shipped, and the two 10-19 posts (Ruyi Firmware, community public infrastructure) were already covered in the mid-October report, so they are not repeated here.

Date: 2026-10-30　Source: openRuyi commit history, llvm23 spec

CORE-V CVW no longer caches invalid PTEs per Svvptc (10-30)

PR #1974 fixes a deadlock that only surfaces under the RVA23 option: previously HPTW would write the result of “a walk landing on a V=0 leaf or non-leaf PTE” into ITLB/DTLB, and subsequent hits on that cache entry would keep triggering page faults from the cached entry until an SFENCE.VMA was executed. The problem is that Svvptc (an RVA23 optional extension) allows the handler to set V to 1 and retry directly without issuing SFENCE.VMA—under this legal usage, an implementation that caches invalid PTEs would fault forever. The fix has the walker itself take the existing FAULT path to report the error from LEAF, writing nothing to the TLB, so the next access re-walks and sees the updated PTE; correspondingly, tlbcontrol no longer checks PTE.V, and the ITLB ENVCFG_ADUE_1 coverage exclusion moves from line 18 to line 16. This is a typical case of “the spec gives you an optional extension, and the implementation must leave a path open for its legal usage.”

Date: 2026-10-30　Source: CVW #1974

CORE-V CVW fixes trace VM fields and quad overflow detection, rv64gc coverage reaches 100% (10-30)

There are 19 commits in the CVW window; besides Svvptc, three more are worth noting. PR #1909 fixes the RVVI trace fields in wallyTracer: reporting of pte, page type, ppn, virtual/physical address, and access type previously carried stale values from “the previous walk” (often the trap handler’s code page on a TLB hit), causing ACT functional coverage to be recorded incorrectly—now it reports the translation actually used by the current access, with ITLB and DTLB walks captured separately, PTE[60:54] shadowed per TLB entry on RV64, the A/D update latch cleared at the end of each walk, and the PC reported from the first parcel when a 32-bit instruction is fetched across two parcels. PR #1906 fixes quadword cacheline overflow detection (align.sv) and adds a regression case. PR #2004 changes code coverage to be counted per configuration, with rv64gc reaching 100%; it also upgrades riscv-arch-test to act4 775be78d4 and syncs the act/sail yaml configs.

Date: 2026-10-30　Source: CVW #1909, CVW #1906, CVW #2004

II. Product and Ecosystem Updates

Qwenputer compiles RV32IM into Qwen3.5-4B weights, using attention state as RAM (10-30)

The experimental model Qwenputer, released by developer Divyansh Agrawal on 10-22, reached a broader audience on 10-30 after being relayed by Chinese media. The approach “compiles” the RV32IM instruction set and its extensions into the weights of Qwen3.5-4B, using the model’s built-in Gated DeltaNet state as precisely addressable RAM, thereby running real programs inside the forward pass—no training required, as the compiler directly writes each weight: attention heads perform table lookups, feed-forward units implement arithmetic via lookup tables, and DeltaNet heads hold memory.

The verifiable gains are concentrated in exact arithmetic: large-integer multiplication rose from 55.0% to 97.5%, large-integer division from 72.5% to 97.5%, addition and subtraction from 87.5% to 97.5%, longer chains of repeated multiplication and division from 90.0% to 100%, and synthetic integer arithmetic from 75.0% to 97.5%; the long-integer benchmark NUPA went from 48.6% to 100%. The project states that this CPU passes the official RISC-V tests and executed roughly 18 million instructions consecutively without error; it also experimentally built an “in-model file system” storing up to 512 files, about 53,000 tokens, in GDN state.

The costs are equally clear: model size grows to about 18.8GB (nearly double the original), each CPU instruction requires generating multiple tokens, so computations that originally took milliseconds may stretch to seconds, and running it requires a dedicated driver rather than loading it like an ordinary model; the project is open-sourced on Hugging Face and GitHub and can run on a single GPU with 24GB of VRAM. The significance of this for the RISC-V community lies not in performance but in “RISC-V as a deterministic execution layer being borrowed by another system”—it demonstrates that the minimal RV32IM ISA is well suited to being formally embedded in heterogeneous substrates.

Date: 2026-10-30　Source: IT之家 report (Sohu reprint), technical analysis

SpacemiT builds Bianbu AgentOS umbrella repo, edge agent stack pinned by submodule (10-30)

spacemit-com opened a new bianbu-agentic umbrella repo and completed its bootstrap: it does not vendor code itself but only pins one commit per component via submodules, so that a full device image can be reproduced from a single SHA. The components listed in the repo form a complete edge agent operating system: agent runtime (YAML-driven session event streams, lifecycle, model invocation, tool/plugin execution and security boundaries, Python), agent-security (tool approval, per-agent synchronized capabilities, securityd signed manifests, including Debian packaging), agent-memory (Rust, L1 session drawer / L2 working drawer / L3 long-term drawer), bibit-intent (intent routing and tool execution: deterministic rules → local inference → cloud escalation), BiBit GUI (Jan-based desktop frontend, Tauri), bibit-voice (KWS wake word, VAD, ASR, served via /run/bibit/audio.sock), bibit-filesearch (local semantic file search, data never leaves the machine) and lxqt-schedule.

What is noteworthy about this split is that “memory” has been made an independent subsystem in three layers, while “security” has been made a resident daemon with signed manifests—both are components that only appear when an agent is taken from demo to deliverable system. For RISC-V edge platforms such as the K series, this means the vendor’s software focus is moving up from “drivers and ROS documentation” to “runtime and system services.”

Date: 2026-10-30　Source: bianbu-agentic repo, README

docs-chip deleted the P1S product documentation and its review tool references: the P1S pages under the Chinese and English power_stone directories, navigation links, and the casing checks, chip path lookup, glossary, system prompt, entity metadata and Copilot instructions in the documentation review agent were all cleaned up. docs-product merged PR #153, updating the hardware resource links for K3 Pico. The former signals product line convergence (a product removed from both documentation and toolchain), while the latter is routine maintenance of delivery documentation.

Date: 2026-10-30　Source: docs-chip commit, docs-product #153

Radxa Linkr adds OBS browser capture guide, initializes linkr-now-skill (10-30)

Four repos in Radxa’s browser-based remote management product line saw pushes within the window: docs added an OBS browser capture guide, linkr-docs and linkr-docs-en were updated in sync, and linkr-now-skill completed initialization (Go). Linkr targets remote out-of-band management for development boards and NAS devices; the OBS capture guide indicates that its video path is beginning to be used as a live-streaming/recording source—a use-case expansion rather than a kernel or firmware change.

Date: 2026-10-30　Source: linkr docs commit, linkr-now-skill

III. In-depth look at domestic teams

Nuclei releases Nuclei Studio VS Code IDE preview (10-30)

Nuclei released the Nuclei Studio VS Code IDE in Shenzhen on 10-30, giving its official development tools two forms: Eclipse and VS Code. The current release is Windows developer preview 0.1.0, with Chinese and English interfaces, installed as a VSIX into an existing VS Code (requires 1.134.0 or later) without conflicting with installed extensions; underneath it still depends on Nuclei Studio IDE 2025.10.

The compatibility strategy is “no rewrite, copy over as much as possible”: the VS Code version can directly import Eclipse-version projects, has built-in cproject compatibility handling, and is ready to develop as soon as it opens; the new-project wizard matches the Eclipse version (choose vendor, SoC, board, SDK), and SDKs and BSPs are still distributed as NPK packages, interchangeable between the two versions. Debugging supports four methods — OpenOCD, J-Link, QEMU, and NucleiModel — all going through CDT gdbtarget, with breakpoints, stepping, variables, call stack, memory and peripheral register views, serial monitor, and disassembly all present, plus a new Live Watch. There is no wall on the AI side: regular AI coding assistants work as soon as installed, compatible with Kimi, GLM, DeepSeek, and Qwen; the official demo uses Kimi Code to take over the project with @helloworld, turning a CoreMark project into an AES-256-CBC demo in one sentence, then debugging it directly in QEMU with PASS printed over serial. The roadmap lists Linux and macOS support, profiling, code coverage, ETrace, flash programming, and more AI assistants.

For the domestic RISC-V developer ecosystem, the practical significance of this step is “entry-point migration”: slow, bloated Eclipse startup has been a long-standing complaint, while the VS Code side can conveniently connect to local or cloud models. Toolchain documentation kept pace with the 2026.10 release — xlmodel docs, toolchain docs, English versions of the QEMU XEC Ethernet guide, Studio’s npk / gdb trace / big-endian debugging notes, and English versions of the xxlvfbf / xxlvw / xxlvqmacc custom extension docs, 5 commits in total.

Date: 2026-10-30　Source: Design & Reuse release, nuclei-tool-guide commits

Sophgo LLM-TPU supports InternVL3 / LLaMa3, fixes Qwen3-ASR decoding degradation (10-30)

LLM-TPU merged PR #178 (support for InternVL3, LLaMa3, and optimization of Qwen2_VL) and #182. The latter is a real defect worth recording: forward_next copies the output of lm_head via d2d into the input_ids of embed_cache. When --do_sample is set and lmhead_with_topk=false, lm_head outputs the full [1,151936] logits (607232 bytes); copying that into a 4-byte token-id buffer corrupts the embedding lookup at every decoding step, degrading output into repeated garbage tokens (for example, turning language Chinese<asr_text> into languagelanguage...). The fix is to feed the token_id from greedy_head (4 bytes) in that branch instead, aligning with Qwen2_VL’s forward_next; the author compared token by token against HF on both CV84X6 and 1684X boards and got identical results, and reverting the change reproduces the original garbage output, confirming causality.

There is also one sophon-tools update: se-rag-core changes the status marker to auto-refresh every 24 hours, bumping the version to 1.5.4. In the same window, 10 sophgo repositories — libsophon, middleware, osdrv, linux_5.10, build, sophpi, sophon-tools, and others — were pushed in a batch within the same minute on 10-31, a bulk SDK-side sync with no individual feature notes.

Date: 2026-10-30　Source: LLM-TPU #182, LLM-TPU #178, sophon-tools commits

DAMO XuanTie and ESWIN: zero new organization-level development in the window (11-02)

XUANTIE-RV had zero pushes in the window; the most recent was torq-tile on 10-29 14:14 (Beijing time, before the window start), with llvm-project and bcc stopped at 10-27 and 10-21 respectively; ESWIN’s eswincomputing last pushed linux-stable on 10-19. Neither had verifiable new development output within the 72-hour window. It should be noted that this does not mean the product lines went silent — XuanTie’s C950 multi-core interconnect / AI inference / server Java progress and automotive-grade E908A announced at the 10-19 summit were already covered in the late-October issues and are not repeated here.

Date: 2026-11-02　Source: XUANTIE-RV, eswincomputing

IV. Special Chapter on Embodied Intelligence and Robotics

SpacemiT Adds Unified Robotic Arm Control Framework, 85 Files Cover Calibration/Diagnostics/Kinematics (10-30)

spacemit-robotics/manipulation committed 85 files at once, +8605 lines, establishing a unified robotic arm control framework. The directory structure is split by capability: calibration contains charuco calibration, hand-eye calibration CLI, and sampling tools; diagnostics has arm_check and an operator CLI; kinematics provides URDF-based forward kinematics; motion is the device service and CLI (device_service.cpp, 234 lines); bindings/python provides the spacemit_manipulation client and operator support layer; the build side uses CMake’s driver_modules to organize driver modules.

The judgment this structure reveals: the vendor treats the robotic arm as a system component “with calibration, diagnostics, kinematics, and a service interface,” not as a piece of sample code. Hand-eye calibration and charuco are unavoidable prerequisites for real-machine deployment, and arm_check and the device service are the minimal interfaces needed to connect the robotic arm to an agent/upper-layer scheduler. For the RISC-V robotics stack, this kind of “engineering skeleton” demonstrates deployment progress better than a single algorithm demo.

Date: 2026-10-30　Source: manipulation commit

SpacemiT dice_arena Adds Integrated Dice Game Application (10-30)

dice_arena added an integrated dice game application, alongside pushes of pyagxarm (robotic arm SDK bindings) and humanoid-related repositories in the same batch. In terms of content, dice_arena is a demo-type application that strings together the perception-decision-execution chain with a low-degree-of-freedom task; its value lies in giving the entire stack a reproducible end-to-end example.

A note on scope: within the window, the pushed_at of 5 repositories under spacemit-robotics was updated, but humanoid_common and humanoid_unitree_g1 had no new commits on the main branch within the window—these were pushes to other branches; the substantive commits of humanoid_common should be based on the previous cycle’s record and are not recounted in this issue.

Date: 2026-10-30　Source: dice_arena commit, spacemit-robotics

SpacemiT docs-ros Adds English RealSense Guide, Aligns Chinese and English Docs (10-30)

docs-ros added an English version of the RealSense guide and aligned the documentation structure. Previously, the site’s depth camera content was mainly in Chinese, with no corresponding entries on the English side; after this addition, the visual perception chain on the K3 platform (camera integration, calibration, and interfacing with ROS 2 nodes) is consistent across both Chinese and English. For overseas developers and domestic teams building export solutions, this kind of documentation alignment is often a prerequisite.

Date: 2026-10-30　Source: docs-ros commit

V. Summary and Trend Observations

1. On the kernel side, the keyword is shifting from “support” to “scheduling by hardware capability.” Linux 7.4 moves the determination of fast unaligned access from compile time to runtime; an optimization that in the 7.3 era could only remain in a custom kernel can now be carried by default in distribution kernels, and Tenstorrent’s self-measured bandwidth gain has an upper bound of 11%. The “B” extension and Zic64b reporting for hwcap/hwprobe merged in the same batch are precisely the data sources for this kind of runtime decision. For the several domestic RISC-V distributions, this is a zero-cost gain, but the precondition is that chips report truthfully in hwprobe—hardware vendors reporting capabilities fully benefits users immediately more than doing one more microarchitectural optimization.

2. The XiangShan frontend has entered the “prefetch queueing” stage. Issue #6691 logically moves iprefetch from ICache-top’s “1 per cycle” into the FTQ, first solving loss and blocking, and only then discussing algorithms like PDIP; the accompanying MBTB/VBTB fixes indicate that the bottleneck has shifted from “fetch bandwidth” to “metadata precision.” Taken together, frontend optimization is moving from adding buffers to “treating prefetch as a first-class schedulable resource”; the gains from such changes can only be verified under long-term workloads, and short-term benchmarks may not look good.

3. Differential verification is beginning to pay a performance cost for accelerator operators. All 9 difftest commits over three days revolve around MMA: FP8 product packing, GPU-side comparison, CUDA pipelining, XDMA relay packing, and LightSSS support for the CUDA backend. For RISC-V AI cores to reach mass production, verification throughput must keep up with operator complexity; otherwise “computing correctly” will become “never finishing computing.” The direction of this group of changes is more worth recording than the gain of any single commit.

4. Both sides of the toolchain are setting baselines simultaneously. openRuyi introduces llvm23 and sets the default ISA for the riscv64-openruyi-linux triple to RVA23U64; Nuclei migrates its IDE from Eclipse to VS Code and syncs xlmodel, the toolchain, and big-endian debugging documentation to 2026.10. The former determines “what code is generated by default,” and the latter determines “where developers enter from”; both are long-cycle decisions with no short-term visible effect, but they will influence default choices over the next one to two years.

5. Domestic output this cycle is concentrated on Ascend and Nuclei, with the route moving up from boards to the system stack. Ascend’s substantive work is model support and the fix of a decoding degradation bug (logits copied into a 4-byte token buffer, causing each decoding step to corrupt the lookup table); such defects can only be located by token-by-token comparison on real hardware; Nuclei switches its toolchain entry point to VS Code and incidentally completes AI assistant integration. DAMO XuanTie and ESWIN had a gap within the window, while SpacemiT advanced both the Bianbu AgentOS umbrella repository and a robotic arm control framework—one company advancing “on-device agent runtime” and “robotic arm calibration/diagnostics/kinematics” in parallel shows that the focus of its RISC-V software stack is shifting from drivers and documentation to a deliverable system layer. The news side this issue is thin: after deduplication of Chinese and English queries, there are only three substantive new items—Linux 7.4, Qwenputer, and Nuclei Studio—with the rest being stock-market pieces, consumer electronics, and reposted old articles; the open-source side remains the main body.

Appendix

Complete Source List

Source Verification Table

Source Verification Result
Google News (27 queries in Chinese and English) After deduplication within the window, 3 substantive new items: Linux 7.4, Qwenputer, Nuclei Studio; the rest were stock market pieces, consumer electronics, reposted old articles, and gambling-related noise, which were excluded
Hacker News 2 items: Linux 7.4 (valid); an Ubuntu blog on post-RVA23 evolution (original dated 9-15, an old article, not counted as an item)
Phoronix 1 RISC-V-specific item in the window (Linux 7.4); the rest covered graphics cards and storage subsystems
CNX Software, LinuxGizmos, LWN No RISC-V-specific hits in the window
riscv.org official blog No new posts; the homepage banner is a call-for-papers deadline notice for the North America Summit
openRuyi official news page Latest is still the 2026.09 edition (9-30); the October edition has not been released, and the two 10-19 posts were covered in a previous report
openRuyi main repo 6 commits, including the addition of llvm23 23.1.4 and a security fix for ollama 0.40.7
riscv100.top inspection Notable: 1 new 10-17 record (XSCC 2.0 on XiangShan KMHv3 RTL 3GHz, int 68.41, fp 76.95), 2 dropped off the leaderboard; no changes to What’s New or committee members
RISC-V member company website inspection 391 companies inspected (67 failed to fetch); updates were all routine homepage content from universities and institutions, with no substantive product, funding, or architecture developments
Key GitHub repositories XiangShan 4, difftest 9, NEMU 2, XSCache 1, GEM5 1, CVW 19, CVA6 0, openRuyi 6, Sophgo 5, SpacemiT 11, Nuclei 5, Radxa Linkr 4
Espressif 58 repo pushes in the window, part of daily batch syncing; no RISC-V-specific changes
DAMO XuanTie, ESWIN Zero organization-level pushes in the window; most recent commits dated 10-29 and 10-19 respectively