Research window: 2026-11-03 05:00 ~ 2026-11-04 05:00 (Beijing time, 24 hours).

Sources: Google News aggregation (11 query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, the openRuyi official news page and main repository, website inspections of RISC-V International member companies (391 companies), the riscv100.top leaderboard inspection, as well as commit and release searches on GitHub for organizations and key repositories including XiangShan, NEMU, difftest, XSCache, GEM5, CORE-V CVW, CVA6, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, and Radxa Linkr.

This Issue’s Index

  • Today’s Focus: XuanTie C950 wins the “China Chip” Annual Major Innovation Breakthrough Product Award; ten customer chips powered by XuanTie cores win awards on the same list (11-03)
  • RISC-V 100 Leaderboard Updates
    • Backfilled 10-10 record: XSCC 2.0 on SpacemiT K3 X100, SPEC CPU2026 Rate int 1.01, fp 1.13 (11-04 inspection)
    • What’s New adds two announcements for K3 X100: version progress and leaderboard entry (combined narrative, same day)
  • I. Open Source Community and Software Ecosystem
    • XiangShan TAGE stores alt information in meta; training reads occur only on prediction or result errors (11-03)
    • XiangShan fixes CBO opcode concatenation error: CBIE’s inval-to-flush was mistakenly synthesized as cbo.zero (11-03)
    • XiangShan StoreQueue and LoadUnit four fixes: CBO zero enqueue, cross-16B forwarding mask, MdpHit determination, rollback information loss (11-03)
    • XiangShan adds BPU counters and CROB debug signals, refreshes README and adds AGENTS.md for AI coding agents (11-03)
    • openRuyi fifteen commits: TileLang and Triton RuyiAI packages merged into repo, buddy-mlir and kernel debuginfo support follow up (11-03)
    • revyos/linux twenty configuration commits merged: K3 UFS and DC, ESWIN EIC7700, linuxboot and cross-compilation CI (11-03)
    • difftest splits matrix verification’s writeback and completion events (11-03)
    • Four institutions including Ruhr University Bochum benchmark four randomized caches on RISC-V multi-core SoC (11-04)
    • OpenBSD 8.0’s RISC-V improvements reinterpreted by media (released 10-20, reported 11-03)
  • II. Product and Ecosystem Updates
    • onsemi completes acquisition of Codasip’s low-end RISC-V processor business; Codasip pivots to CHERI (reported 11-03)
  • III. Deep Dive on Domestic Teams
    • “Powered by XuanTie” among the co-awarded list: from 3D near-memory computing to automotive-grade and Wi-Fi routers (11-02)
    • Sophgo cvi_rtt releases 2026.11.03 weekly version (11-03)
    • SpacemiT model-zoo-vision tightens result contract and unifies embedding normalization (11-03)
    • DAMO XuanTie, ESWIN, Nuclei, Espressif organizational updates within the window (11-03)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • humanoid_common declares whole_body build dependencies (11-03)
    • ros2_simulation improves G1’s RGBD relocalization with textured ground (11-03)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Source Verification Table

Today’s Focus: XuanTie C950 Wins “China Chip” Annual Major Innovation Breakthrough Product Award; Ten Customer Chips Built on XuanTie Cores Also Honored (11-03)

On November 2, the 2026 “China Chip” Integrated Circuit Industry Promotion Conference — themed “Intelligence Ignites the Chip Journey, Collaboration for Shared Growth” — and the 21st “China Chip” Outstanding Product Selection Results Announcement Ceremony were held in Hengqin, Zhuhai. XuanTie C950, developed by Alibaba DAMO Academy, received the “Annual Major Innovation Breakthrough Product Award.” This award has the highest threshold in this year’s selection, specifically recognizing landmark products that achieve major breakthroughs in core technologies and possess international competitiveness; Jiwei.com released the award news on the afternoon of November 3. In the previous edition, XuanTie received the “Outstanding Supporting Service Enterprise” and “RISC-V Ecosystem Promotion Demonstration Case” awards. Moving from ecosystem-promotion awards to product-innovation awards — the shift in the award criteria itself speaks to this IP vendor’s position in the industry.

The official C950 specifications are unchanged from its March launch this year: 8-instruction decode, 16-stage pipeline, an out-of-order window of over 1,000 instructions, a maximum clock speed of 3.2GHz, and a SPECint2006 single-core score exceeding 70 for the first time. What’s new this time are three sets of deployment figures: cumulative shipments of the full XuanTie series exceed 6 billion units, with over 400 customers and more than 1,000 licenses; C950 supports all standard and optional extensions of RVA23.1 and natively integrates CoVE confidential computing; the Vector and Matrix AI engines share a unified address space with the CPU, and the company claims it is the first to enable native CPU support for running models such as Qwen3.8-Flash-Next, Qwen3.5-4B, Qwen3-235B-A22B, and DeepSeek V4-Flash, with cloud networking and cloud storage performance under workloads such as MySQL, Redis, and Nginx improving by more than 30% over some mainstream products.

More noteworthy than the main award is the customer list on the same roster: Dongfang Suanxin’s 3D near-memory computing chip DF1000 (XuanTie C908 plus C906) also received the “Annual Major Innovation Breakthrough Product” award; Allwinner’s T536 industrial SoC (E907), Jiangyuan Technology’s cloud inference chip D1 (C908 plus E907), Wuqi’s WQ9301 Wi-Fi router chip (E907), and Hongsi’s HSRU3 reconfigurable algorithm chip (E906) received “Outstanding Technological Innovation Product” awards; Qingwei Intelligent’s reconfigurable AI chip TX81 (C908) and Taixin’s TXW82X tri-mode audio-video chip received “Outstanding Market Performance Product” awards; Jiangxinchuang’s D12X smart display MCU (C906), Jiuchen’s TD1601 series MCU (E906), and Maitexin’s MEGA188 edge AI chip (E902) received “Chip Fire Rising Star Product” awards. These ten chips span entirely different markets — near-memory computing, industrial control, cloud inference, wireless connectivity, reconfigurable AI, and display drivers — yet all use four tiers of cores from the same IP family. This demonstrates the coverage density of the XuanTie product line far better than a single flagship winning an award.

Date: 2026-11-02 (conference) / 2026-11-03 (report)　Source: Jiwei.com report (reposted by Sohu)

RISC-V 100 Leaderboard Updates

This inspection period is judged to have significant changes, placed earlier in the main text per editorial policy.

New leaderboard entries (one each in Cross-Architecture · SPEC CPU2026 and the RISC-V channel · SPEC CPU2026): 10-10 XiangShan Compiler Team (XSCC) / SpacemiT XSCC 2.0 on SpacemiT K3 X100 2.4GHz int 1.01, fp 1.13 (rate/ref, Completed); compared with the previous record for this platform (07-30, XSCC 1.1), int +12.2%, fp +5.6%. The record date of 10-10 predates this inspection day, so it is a backfilled entry and should not be read as a new result from that day; compared with the 07-30 record backfilled yesterday, the same platform and same compiler span a major version, with the integer score rising from 0.9 to 1.01 and floating-point from 1.07 to 1.13 — the only paired “same-platform before-and-after comparison” in this round of backfills.

Two new What’s New items: SpacemiT K3 X100 XSCC 2.0 SPEC CPU2026 Rate (corresponding to the leaderboard entry above), and SpacemiT K3 X100 Version Progress Now Available (a version-progress page newly added to the site); per editorial policy, these are described together with the leaderboard entry and not counted separately. The three Upcoming items remain in Preparing status, and there are no additions or removals among committee members.

Date: 2026-11-04　Source: riscv100.top Cross-Architecture SPEC CPU2026, riscv100.top RISC-V Channel SPEC CPU2026, riscv100.top Homepage

I. Open-Source Community and Software Ecosystem

XiangShan TAGE stores alt information in meta, training reads occur only on misprediction or result mismatch (11-03)

PR #6800 addresses the conflict in the TAGE predictor where training reads and prediction reads contend for the same storage. Previously, the former needed the alt-branch information to decide how to train, and this information was also read during the prediction stage, with both paths colliding on the same set of table entries. The change additionally stores alt information in meta, so the training side no longer reads it on every prediction, and only initiates a training read when TAGE mispredicts or when the actual branch outcome differs from the prediction.

The benefit of such a change is not reflected in IPC, but rather in removing a high-frequency read path from the critical path: the predictor must produce a result every cycle, whereas training occurs only once per misprediction, and moving work to low-frequency events is the most typical trade-off in branch predictors. For XiangShan, which is pushing for high frequency, the saved port contention is worth more than the saved table entries.

Date: 2026-11-03　Source: XiangShan #6800

XiangShan fixes CBO opcode concatenation bug: CBIE’s inval-to-flush mistakenly synthesized as cbo.zero (11-03)

PR #6754 is a decoding bug with fairly serious consequences. In cache block operation (CBO) instructions, the operation type should have selected the complete opcode as a whole, but the code performed a bitwise OR of the “full CBO opcode” with the “base opcode.” When a CBIE request converts inval to flush, the OR operation synthesized cbo.inval and cbo.flush into cbo.zero—changing the semantics from “invalidate this block” to “zero this block.”

The difference is not just cache state: inval merely discards, whereas zero writes data. A zeroing with data landing on a line being used by another hart or about to be written back is silent data corruption, and it is triggered only under specific operation sequences, so neither benchmarks nor routine regression can catch it. The author states the cause very directly in the commit message; this kind of bit-field error—”should have selected but wrote an OR”—is especially easy to make in RISC-V’s newly added CBO extension, because the opcodes themselves are hierarchical.

Date: 2026-11-03　Source: XiangShan #6754

Four XiangShan StoreQueue and LoadUnit fixes: CBO zero enqueue, cross-16B forwarding mask, MdpHit determination, rollback information loss (11-03)

Four memory-access-related fixes were merged on the same day, together constituting a concentrated troubleshooting pass over the load-store path. PR #6762 makes flush wait for CBO zero to finish enqueueing first, preventing zeroing operations from being lost when the queue is flushed; PR #6718 fixes the forwarding mask for cross-16-byte unaligned accesses, which hit two table entries simultaneously and forward wrong bytes if the mask is computed incorrectly; PR #6714 fixes the MdpHit determination condition when waitSqidx has retired, a state judgment on a timing boundary; PR #6678 fixes LoadUnit rollback information being overwritten by a later instruction under the same RobIdx.

What the four have in common is that they all fail only under specific interleavings: unaligned access combined with forwarding, retirement and hit determination in the same cycle, two consecutive loads with the same RobIdx triggering replay. XiangShan has clearly intensified its investment here recently, which is also related to the wide memory-access paths introduced by the Matrix extension—the wider the path, the more boundary conditions.

Date: 2026-11-03　Source: XiangShan #6762, #6718, #6714, #6678

XiangShan adds BPU counters and CROB debug signals, refreshes README and adds AGENTS.md for AI coding agents (11-03)

PR #6777 adds several performance counters related to s2_override in the BPU; these events previously occurred but were not counted, so they were invisible in performance analysis. PR #6749 adds decode signals in CROB for the remaining writeback counts of former/latter, with the commit message stating that these encodings were originally compressed to save area and the decoded results are now exposed for backend debug mode. Both are “observability” investments that do not change functionality but determine whether problems can be located when they occur.

PR #6849 refreshes the README and adds AGENTS.md at the repository root. The latter is a project description file for AI coding agents, specifying build methods, code style, and commit conventions. An RTL project actively maintaining such a file indicates that agents are already participating by default in its daily development workflow.

Date: 2026-11-03　Source: XiangShan #6777, #6749, #6849

openRuyi fifteen commits: TileLang and Triton RuyiAI packages enter the repo, buddy-mlir and kernel debuginfo support follow (11-03)

The openRuyi main repository merged fifteen software package commits that day, most notably three new packages: python-tilelang-ruyiai, python-triton-ruyiai, and buddy-mlir, with commit messages directly stating “added as RuyiAI packages.” These three previously existed only in the upstream repositories of the RuyiAI stack; now they enter openRuyi as distribution SPECs, meaning this RISC-V AI software stack is beginning to follow the path of “entering the distribution, installable by the package manager” rather than being distributed via source build scripts. A follow-up commit fixing the buddy-mlir source path was also merged the same day.

The rest are engineering updates: simdjson upgraded to 5.0.8 and switched to running upstream tests offline via Ninja to avoid network access during builds; openruyi-linux-build now supports generating debuginfo packages, with kernel modules changed to install unstripped and uncompressed, left to find-debuginfo, while CONFIG_DEBUG_INFO_SPLIT is marked unsupported to ensure debuginfo packages are valid; there is also a batch of supplementary packages for rust-side sval and phf-related crates. The debuginfo item matters considerably for those doing performance analysis and production troubleshooting—previously kernel modules were stripped, so stack traces could only show addresses with missing symbol names.

Date: 2026-11-03　Source: openRuyi commit history

revyos/linux merges twenty configuration commits: K3 UFS and DC, ESWIN EIC7700, linuxboot and cross-compilation CI (11-03)

The revyos 7.3.y branch merged twenty kernel configuration commits at once that day, all with the same timestamp, constituting a concentrated synchronization. On the hardware side, newly added or enabled items include: SpacemiT K3’s UFS and display controller, K3’s USB3 PHY and a whole group of Type-C/TCPM/UCSI/FUSB301/DP alternate mode, ESWIN EIC7700’s ARCH and DWMAC Ethernet and pinctrl, AST display, LM63 temperature sensor, and Banana Pi F3’s K1 USB2.

On the platform capability side, two items are more critical: a new linuxboot configuration, and adding both cross and native build pipelines to CI. The former means this distribution kernel is beginning to consider scenarios where it is loaded as linuxboot firmware; the latter solves the long-standing problem that kernel configuration changes cannot be verified at commit time. There is also a PicoHeart errata switch and enabling the NVMEM layout for ONIE TLV, the latter being the asset tag format used for batch deployment of switches and network devices.

Date: 2026-11-03　Source: revyos/linux commit history

difftest splits matrix verification’s writeback and completion events (11-03)

PR #1025 splits the matrix unit’s AMU events into two categories: “writeback” and “completion.” Previously a single event carried both semantics, and the reference model and design under test could easily mistake “data has been written back” for “instruction has completed” or vice versa under out-of-order interleaving, causing the checker to pass intermediate states. After the split, the two event types each carry a sequence number, and verification can align by semantics.

This is a necessary step toward making matrix extension verification usable: for long-latency instructions like MMA, completion order and writeback order are inherently inconsistent, and expressing two things with one event inevitably leads to misjudgment in multi-core or replay scenarios. This was the only commit in that repository that day.

Date: 2026-11-03　Source: difftest #1025

Four institutions including Ruhr University Bochum benchmark four randomized caches on a RISC-V multi-core SoC (11-04)

A joint team from Ruhr University Bochum, the Max Planck Institute for Security and Privacy, and Georgia Tech released the preprint “Randomized Caches in Hardware: Challenges and Trade-offs” (arXiv, October 2026, CC BY 4.0), authored by Xinrui Wang, Pascal Kosak, Christof Paar, Daniel Genkin, Yuval Yarom, and Anirban Chakraborty. Randomized caches defend against side-channel attacks by scrambling the address-to-cache-location mapping; previous schemes mostly stayed at the architectural description level, and no one had systematically discussed the pitfalls of hardware implementation.

The team implemented all four designs—CEASER-S, ScatterCache, SassCache, and MIRAGE—as the last-level cache of the same multi-core out-of-order RISC-V SoC, built a complete FPGA prototype, and ran the full SPEC CPU 2017 rate and GAPBS workloads. According to their statement, this is the first horizontal evaluation of these four designs on the same full-system hardware platform. The paper focuses on implementation difficulties and trade-offs and does not give a quantitative performance-overhead comparison in the public abstract—this is worth noting, as cost data for security mechanisms often hides in the body tables.

Date: 2026-11-04　Source: IndexBox coverage of the paper

OpenBSD 8.0’s RISC-V improvements reinterpreted by media (released 10-20, reported 11-03)

OpenBSD 8.0 was released on October 20, and on November 3 media re-examined its RISC-V portions, which deserve a separate note because this version’s riscv64 platform increments focus on architectural features rather than drivers: the kernel begins probing CPU extensions and reporting them to user space via elf_aux_info’s AT_HWCAP and AT_HWCAP2, so user-space programs can now dispatch code paths by hardware capability; the kernel adds V vector extension support; implements bounce buffers; supports the RISC-V advanced interrupt architecture and adds imsic and aplic drivers; and adds Sstc timer extension support. The same version also retired the Loongson port.

For RISC-V distributions, hwcap reporting is more fundamental infrastructure than any single-point optimization—without it, user space can only guess at branches based on compile-time assumptions. The landing of AIA and Sstc means this board’s interrupt and timer paths are beginning to shed old interrupt-controller assumptions.

Date: 2026-11-03　Source: OpenBSD 8.0 release notes

II. Product and Ecosystem Developments

onsemi completes acquisition of Codasip’s low-end RISC-V processor business, Codasip pivots to CHERI (reported 11-03)

On November 3, media reported that onsemi has completed its acquisition of Codasip’s low-end RISC-V processor business for approximately $14.5 million, with about ninety percent of the price already paid, involving 27 of Codasip’s roughly 260 employees, along with broad licensing of the Codasip Studio processor design tool. The deal itself was announced in April and closed in May; the value of this report is that it fills in the details on price and headcount.

After the deal, Codasip’s direction is already clear: abandon general-purpose CPU IP licensing and pivot to memory-safe processors based on CHERI capability hardware, selling chips rather than designs for defense and critical infrastructure. The reference point for this path is another RISC-V company, SCI Semiconductor, whose CHERI processor raised £5 million in September. For the RISC-V IP market, this is a typical shakeout—the general-purpose core licensing business is increasingly difficult amid oversupply and price wars, and those who remain are either buyers like onsemi who use cores in their own chips, or sellers who have found a differentiated security narrative.

Date: 2026-11-03　Source: Jon Peddie Research report, Codasip April spin-off announcement

III. Deep Dive on Domestic Teams

“Powered by XuanTie” in the Same Award List: From 3D Near-Memory Computing to Automotive-Grade and Wi-Fi Routers (11-02)

Looking at the XuanTie C950 award alongside the customer chips on the same list reveals the actual distribution of this IP product line. The top tier is Dongfang Suanxin’s DF1000, which uses C908 plus C906 to build a high-energy-efficiency software-defined near-memory computing 3D chip, sharing the “Annual Major Innovation Breakthrough Product” award with C950—showing that high-end RISC-V can already enter form factors like 3D stacking that place extreme demands on energy efficiency and interconnect. The second tier is four “Outstanding Technological Innovation Products”: Allwinner T536 high-performance smart industrial SoC uses E907, Jiangyuan D1 cloud inference chip uses C908 plus E907, Wuqi WQ9301 Wi-Fi router chip uses E907, and Hongsi HSRU3 reconfigurable algorithm chip uses E906—corresponding respectively to four unrelated tracks: industrial control, cloud inference, wireless connectivity, and cryptographic algorithms.

Further down is the mass-production scale tier: Qingwei Intelligent TX81 reconfigurable AI chip uses C908, and Taixin TXW82X tri-mode audio-video chip uses the E series, both winning “Outstanding Market Performance Product”; Jiangxin Chuang D12X smart display MCU uses C906, Jiuchen TD1601 series MCU uses E906, and Maitexin MEGA188 edge AI chip uses E902, all winning “Xinhuo Emerging Product.” Four core tiers from C908 to E902 cover ten chips, and none of them are fighting price wars in the same market—this is the concrete footnote to the two figures of 6 billion units shipped and 400 customers.

Date: 2026-11-02　Source: Jiwei report (reposted by Sohu)

Sophgo cvi_rtt Releases 2026.11.03 Weekly Version (11-03)

Sophgo’s cvi_rtt repository released the 2026.11.03 weekly version that day, with a commit message consisting of only a single line with the version number. This is a weekly-tagged RT-Thread board support repository that had long gone without updates; this time it restarted versioning with two commits, “initial” and “weekly rls,” indicating that this maintenance line running RT-Thread on the Sophon platform is still advancing on schedule, though there was no readable functional increment that day.

Date: 2026-11-03　Source: sophgo/cvi_rtt commit history

SpacemiT model-zoo-vision Tightens Result Contracts and Unifies Embedding Normalization (11-03)

PR #113 tightened interface robustness for the vision model library: failed result responses are now rejected outright rather than continuing with an error; the legitimate state of “successful empty result” is allowed; output vector reads are unified under finite-value checks; and the Python-side type extractor is tightened. The same commit also changed the normalization handling for embeddings. Changes like these don’t show up in model accuracy or throughput numbers, but they determine whether upper-layer business logic receives half-baked data under abnormal inputs.

Date: 2026-11-03　Source: spacemit-com/model-zoo-vision #113

DAMO XuanTie, ESWIN, Nuclei, Espressif Organizational Activity Within the Window (11-03)

DAMO XuanTie had zero new development at the organizational level within the window, with the most recent push still being torq-tile on October 29; ESWIN likewise, with the latest being linux-stable on October 19. Nuclei had only one push to the nuclei-tool-guide documentation repository, with no substantive changes to the SDK or IDE. Espressif had 36 repository pushes that day, but all were routine maintenance of the ESP-IDF ecosystem (esp-idf, esp-matter, esp-protocols, etc.); the two RISC-V-related ones were esp32s31-bt-lib and esp-vision, which are firmware and vision library updates for C-series chips, with no new information at the chip architecture level.

Date: 2026-11-03　Source: XUANTIE-RV, eswincomputing, Nuclei-Software, espressif

IV. Special Chapter on Embodied Intelligence and Robotics

humanoid_common Declares whole_body Build Dependencies (11-03)

PR #27 added the build dependency declaration for whole_body to humanoid_common. Previously, under parallel builds, the whole-body control module could be compiled before its dependencies were ready, manifesting as randomly failing link errors rather than stable compile errors—making diagnosis very costly. Fixes like this are nearly invisible to users, but are essential for CI stability.

Date: 2026-11-03　Source: spacemit-robotics/humanoid_common #27

ros2_simulation Uses Textured Ground to Improve G1’s RGBD Relocalization (11-03)

ros2_simulation that day fixed a real-world problem with the G1 humanoid’s RGBD relocalization in MuJoCo: solid-color ground lacks visual features, so SLAM easily loses relocalization in corridor-style simulation scenes. The change shares the same ground texture across both the MuJoCo rendering path and the RGBD ray-casting path, ensuring the simulated image and the depth map see the same texture set, switches the default map library to a textured version, and updates the mapping and localization examples accordingly.

Changes like this look trivial, but they are actually key to separating “the algorithm doesn’t work” from “the scene has no features” in simulation: a large portion of robot vision algorithm failures in simulation come from inconsistency between rendering and sensor models, not from the algorithm itself.

Date: 2026-11-03　Source: spacemit-robotics/ros2_simulation commit history

V. Summary and Trend Observations

1. XuanTie’s information value this period lies in the “list,” not the “award.” C950 winning an award was expected; the real increment is that ten customer chips on the same list cover four core tiers from C908 to E902, spanning six markets: near-memory computing, industrial SoC, cloud inference, Wi-Fi routers, reconfigurable AI, and display drivers. This shows that XuanTie’s revenue structure has shifted from “selling cores to a few large customers” to “a long tail spread across tiers,” and the 6 billion units and 400 customers are the natural result of this structure. On the same day, XuanTie had zero pushes on the repos side, contrasting sharply with the density on the news side—once a product line matures, public repositories are no longer the primary observation window.

2. XiangShan’s focus this day was “finding bugs,” not “adding features.” Six of the nine commits were fixes, among which the CBO opcode being erroneously merged into cbo.zero by an OR operation is a serious decoding defect that silently corrupts data, while the four commits on StoreQueue and unaligned forwarding concentrated on boundary conditions triggered only by specific interleavings. The common trait of such problems is that neither benchmarks nor routine regression can find them—only formal methods or directed stimulus can. For teams using XiangShan to prototype chips, this is a reminder: verification investment must keep pace with feature expansion, especially for new extensions like CBO and matrix.

3. openRuyi pulling RuyiAI components into the distribution is the dividing line where this stack goes from “project” to “product.” The RuyiAI packages for TileLang and Triton, along with buddy-mlir, entering the repository as SPECs means users can install them via the package manager rather than building from source by following docs; the same-day completion of kernel debuginfo support makes stack traces for online performance issues usable for the first time. These two things happening on the same day point in the same direction: this distribution is filling in “operability,” not just “it runs.”

4. revyos merging twenty configuration changes at once significantly broadens K3’s platform support surface. UFS, display controller, the full USB3 and Type-C group, ESWIN EIC7700’s network ports and pinctrl, plus linuxboot configuration and the CI cross-compilation pipeline, show that this distribution is moving from “the board boots” to “complete system peripherals and verifiable changes.” The linuxboot item deserves particular attention, as it corresponds to a class of deployment scenarios that load the kernel as firmware.

5. Security papers and an acquisition appearing on the same day is no coincidence. On one side, four institutions implemented four randomized cache designs into the same RISC-V multicore SoC for side-by-side evaluation; on the other, Codasip sold off its general-purpose core business to pivot to CHERI. Both lines are really saying the same thing: RISC-V general-purpose cores have entered price competition, and what can command a premium is security and specialization. For domestic RISC-V teams, this judgment is more worth remembering than any benchmark score.

Appendix: Complete Source List

Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (11 query sets in Chinese and English, 24-hour window) After deduplication, 4 substantive new items within the window: XuanTie C950 winning the China Chip award, details of the onsemi–Codasip acquisition, RISC-V interpretation of OpenBSD 8.0, and the randomized cache paper; XuanTie’s 6 billion unit shipments, the ESWIN CTO interview, Lanxin Computing, Zijing Semiconductor, Tenstorrent funding, Qwenputer, and Linux 7.4 optimizations were all previously covered items recirculating and were not counted again per deduplication rules; sports livestream spam and stock market pieces were removed in bulk
GitHub organization check (DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openHW, openRuyi, Radxa Linkr) Pushes within the window: Sophgo 7 repos, Espressif 36 repos, SpacemiT 5 repos, space robotics 4 repos, Sipeed 2 repos, revyos 1 repo, CORE-V 4 repos, openRuyi 4 repos; zero pushes from XuanTie, ESWIN, and Radxa Linkr
Key repository commit check (XiangShan, XSCache, NEMU, difftest, GEM5, CORE-V, openRuyi, revyos) XiangShan 9 commits, difftest 1 commit, openRuyi 15 commits, revyos 20 commits all verified commit by commit; the CVA6 main branch became read-only on 10-23, and pushes within the window came from non-default branches, with no new commits
RISC-V International member website sweep Swept 391 sites: 223 unchanged, 100 changed (mostly event pages and homepage redesigns at university and consortium sites), 68 failed to fetch; no substantive product, funding, or architecture release updates
riscv100.top check Notable changes: backfilled the 10-10 XSCC 2.0 on SpacemiT K3 X100 record, merged two What’s New entries on the same day into one narrative, and three Upcoming items remain in Preparing
openRuyi official news page Latest entries are the two 2026-10 pieces on ecosystem infrastructure and firmware (10-19) and the 2026-09 distribution release (09-30); no new version announcements within the window
Hacker News / Phoronix / CNX / LinuxGizmos No new RISC-V entries within the window; LinuxGizmos’ ESP32-P4 compute module (SCINTIX P4) was published on 11-01, before the window, and was not included

Limitations

The news side is thin this issue: Google News was heavily polluted within the window by sports livestream spam, with the top 100 results for several query sets consisting almost entirely of the same batch of SEO pages, which were removed in bulk by title pattern before manual verification. The anonymous rate limit for GitHub organization-level APIs was exhausted midway, so commits for GEM5, llvm-project, CORE-V, and openRuyi were retrieved via the repository commit feed (Atom) as a fallback; as a result, full push lists for some organizations could not be expanded repo by repo. The CORE-V pushes were verified to be on non-default branches, with no commits on the main branch within the window. The 68 failed fetches in the member website sweep were concentrated on domestic sites and pages requiring JavaScript rendering, and do not affect this issue’s conclusions.