Reporting period: October 26, 2026 (Monday) through October 30 (Friday) — 5 working days, 5 daily-brief source sets. The 10-26 issue used a 72-hour window (covering 10-23 05:00 to 10-26 05:00); the other four issues used 24-hour windows. As a result, a small number of items in this week’s highlights fall on dates between 10-23 and 10-25, which is normal coverage for that issue; the original dates are noted in the item titles.

Sources: The daily RISC-V Global Briefs (five issues: 10-26, 10-27, 10-28, 10-29, 10-30); supplemented by a 168-hour window review of followed GitHub organizations and key repositories (the anonymous API quota was exhausted for most of the week, so each repo’s commits.atom was checked individually), dual-source verification for openRuyi (main repo commits and the official news page), a riscv100.top leaderboard sweep, and a sweep of RISC-V International member websites (391 members).

Editorial note: This was the first full working week after the 6th RISC-V China Summit (10-18 to 10-21), and news density dropped noticeably. The main thread shifted from “launches” to “engineering convergence” — XiangShan extended its matrix-extension verification chain down to the FP8 precision layer; openRuyi’s ~130 commits for the week went almost entirely into paying down security debt and building out the virtualization foundation; and domestic teams focused on last-mile-before-delivery items such as firmware signing, TEE documentation, and tooling guides. In the same week, the IP layer saw the week’s most telling transaction: onsemi acquired Codasip’s low-end RISC-V processor business for $14.5 million. In addition, this week’s review found that DAMO XuanTie’s torq-tile repository had 13 substantive commits during the day on 10-28 that were not covered by that day’s brief; this weekly report adds them to Chapter 2 based on the commit records.

I. Weekly Highlights

  • onsemi takes over Codasip’s low-end RISC-V business for $14.5 million, as general-purpose core licensing enters a depreciation channel (10-26): The deal covers only 27 of Codasip’s roughly 260 employees, plus a license to the Studio processor design tool. According to Czech business outlet e15, the amount is $14.5 million, of which about 90% has already been paid. Codasip announced a strategic adjustment on 2026-04-08, divesting its low-end RISC-V processor design business and pivoting to a CHERI-based “cyber resilience” security architecture; the buyer was not named at the time. The company has received EU and Czech national research funding, and in July this year it publicly disclosed more than €119 million in grants and equity support (most of which has not yet been received), so the transaction price has sparked domestic discussion in the Czech Republic. The company’s line is “reasonable restructuring” rather than a fire sale. Jon Peddie Research’s assessment is worth noting: basic processor cores are becoming hard to differentiate and monetize, and the next phase of RISC-V will be shaped more by established semiconductor companies, with value shifting from the instruction set itself to differentiated products and system integration. Sources: Jon Peddie Research, Codasip announcement

  • Claude pushes formal verification down to RISC-V machine code; 180 million lines of proofs across 123 open-source libraries pass checking (10-23, Monday issue window): Anthropic’s Frontier Red Team, together with Theorem Labs, performed formal verification on 123 open-source codebases and 239 test entry points from the Google OSS-Fuzz corpus. The object of proof is not the source code but the compiled RISC-V machine code that actually runs on the CPU. The project generated roughly 1 billion lines of proofs in total, of which 180 million lines passed the Rocq checker; a single 391-line C parsing entry point in cJSON came with 630,000 lines of accompanying proofs. On detection capability, the team planted 7 bugs in a self-built Rust version of the Python interpreter; random testing missed 5, while formal verification caught all of them. On cost, they offer an amortizable estimate: an investment of $134 million could cover 95% of the machine code in the Nix ecosystem by the end of 2027, amortizing to about $14 per downstream software package; proofs for the first 25 libraries and 60 entry points have been open-sourced. The significance for RISC-V lies in the level of the verification target—the entire proof set is built on mathematical models of RISC-V instructions and Linux process behavior written by Theorem, effectively leaving the ecosystem a reusable semantic foundation. The caveat is that it is currently limited to single-threaded, statically linked code with a fixed memory budget. Sources: 36Kr, Tencent News (Xinzhiyuan)

  • XiangShan spends a week extending the matrix-extension verification chain up to the precision-semantics layer (10-27 to 10-30): The reference model NEMU merged feat(ame): support FP8 MMA with FP32 accumulation (#1266) on 10-27, supporting matrix multiply-accumulate with FP8 inputs and FP32 accumulation; the differential verification framework difftest added a synchronized verification build option (#1009) and integer saturation consistency between the CPU and CUDA sides (#1008) in the same week, and on 10-29 to 10-30 changed MMA writeback to bounded pool reuse (#1014) and reused consecutive operand slots (#1016). Three moves in four days point in the same direction: from “comparing fast” to “comparing correctly” to “comparing completely.” The industry implication of this thread is that matrix extensions are a mandatory question for RISC-V to enter AI inference workloads, and the specification is still in progress; by pushing FP8 and integer saturation semantics into the reference model and differential verification now, XiangShan is effectively preparing the “how to verify once the spec lands” step in advance. Sources: NEMU commit log, difftest commit log

  • Qwenputer compiles an RV32IM processor into Qwen3.5 weights, using GDN state as addressable memory (10-28): Released by developer Divyansh Agrawal, this untrained project maps a 32-bit RISC-V CPU directly into model weights: by setting Gated DeltaNet gates to 1, write strength to 1, and keys to one-hot encoding, the GDN heads degenerate into row-addressable storage; then “read register / add / conditional jump” are each mapped to attention heads, feed-forward layers, and DeltaNet heads, with the CPU occupying the 11 layers before Qwen’s 32 layers. The core is RV32IM plus the Zba extension, with a small big-number unit; the project claims 18 million instructions of free-running execution with no errors, and zero mismatches against a reference machine replay across about 230,000 output positions. It runs C and MicroPython, but requires a dedicated driver, RvChat; the benchmark executor runs at about 3,200 CPU tokens/sec on an L4, with an 18.8 GB checkpoint. On DeepMind’s arithmetic set, div_big and mul_big both reach 97.5% (the base model scores 72.5% and 55% respectively). This should not be read as a product announcement: it demonstrates that any deterministic ISA can be compiled into weights, and the barrier to an ISA has never been instruction encoding but the software stack and ecosystem. Sources: Qwenputer project page, Hacker News discussion, Adafruit

  • Post-quantum instruction set extension runs Classic McEliece on Cyclone V, cutting decapsulation cycles by 86.1% (10-29): The paper presents full FPGA validation of a tightly coupled RISC-V instruction set extension: the entire design occupies 10,531 adaptive logic modules on Cyclone V and closes timing at up to 118.89 MHz; under the same asynchronous memory simulation, encapsulation cycles drop 87.4% and decapsulation 86.1%, equivalent to 7.18x the unaccelerated baseline. The gains are highly uneven—the Berlekamp-Massey sub-operation drops from 5,832 cycles to 40 cycles, and Gaussian elimination cuts minimal polynomial generation from 297 to 38 cycles, but over 99% of the remaining decapsulation cost still lies in the Benes permutation network for support-list generation. The most methodologically valuable part of the paper is a rejected approach: adding DMA-assisted instruction mapping for composeinv yielded only 1.0–1.1x improvement in the controlbits phase, because the recursive call structure repeatedly crosses narrow memory boundaries, offsetting kernel-level gains. The authors derive a selection rule from this—when call structure dominates data movement cost, making only the batched kernel faster is ineffective. Sources: Bioengineer, paper DOI

  • ESWIN’s R520A becomes the world’s first multi-core, multi-architecture RISC-V core to pass ASIL-D; consumer AI NAS set for Q4 mass production (10-28): In an interview, CTO He Ning gave three concrete deployment milestones—on the automotive side, EAM2011 is China’s first automotive-grade MCU supporting lightweight AI applications, built on a self-developed 32-bit RISC-V core and already in volume use in display assemblies, in-car wireless charging, and battery management systems; the self-developed CPU IP R520A has passed ASIL-D functional safety certification from TÜV Rheinland in Germany (the earlier R500A was the world’s first RISC-V core to receive ASIL-B certification); on the edge and intelligent computing side, the company partnered with Zspace to launch the world’s first consumer AI NAS based on the RISC-V architecture, planned for mass production and sale in Q4 2026. The company has mass-produced more than 150 products and serves 220 customers. On AI integration, he breaks the path into three options: an external NPU alongside the main controller, entering the AI unit to handle scheduling, and building compute in-house via vector and matrix extensions, with a timeline: it will take another one to two years for the matrix extension specification to mature and reach products, and another two to three years after that for standardized products at scale. Source: 21st Century Business Herald

  • openRuyi sees about 130 commits over five working days, centered on security debt, virtualization foundations, and measurement tooling (10-26 to 10-30): The daily pace was 20, 46, 20, 20, and 20 commits, plus about 10 more during Friday daytime. Content advanced in four phases: early in the week, Go server-side dependencies were filled in (the gobuffalo series, docker libtrust, various SQL drivers); on Tuesday, a batch of cloud-native component updates tagged [security-fixes] (nats-server 2.15.1, moby 29.9.2, etcd 3.7.2, containerd 2.4.2) plus the full introduction of the Sequoia PGP suite; on Wednesday, the entire Samba family was upgraded to 4.25.1 and uniformly migrated to the Waf build; on Thursday, the rust-vmm component family was added as a group (rust-linux-loader 0.14, rust-vm-memory 0.18, rust-kvm-ioctls 0.25, rust-acpi-tables 0.2.1); on Friday, 13 KDE Frameworks 6.31.0 packages, the Vulkan peak benchmark vkpeak, and LLVM 23.1.4 were all brought into the repository. The latest announcement on the official news page is still the 2026.09 release; no new version was released this week, making this rolling maintenance rather than a release sprint. Sources: openRuyi commit log, openRuyi official news page

  • WuQi Micro’s Wi-Fi 6 AP chip WQ9301 reaches volume shipment; cumulative RISC-V core usage exceeds 600 million (10-26 to 10-27): Chongqing WuQi Micro showcased two product lines at the summit: network communications and edge intelligence. WQ9301 uses a RISC-V multi-core architecture, supports 802.11 a/b/g/n/ac/ax, uplink and downlink MU-MIMO and OFDMA, 160 MHz bandwidth, and 1024QAM, with dual-band concurrent PHY throughput up to 3 Gbps; it integrates baseband and RF on a single chip and targets domestic substitution in routers, smart gateways, and FTTR. The edge AI line lands on AI glasses: the WQ7036 series smart audio main controller integrates VAD and KWS, call noise reduction, and low-power Bluetooth; the company says it has been adopted by more than ten brands including INMO, XGIMI, NIMO, Jianan, Looktech, LOHO, and VITURE. The Looktech product launched at the SILMO show in Paris on 10-15 uses this solution with a built-in EEG sensor and six-axis IMU, with the whole device kept under 30 grams. Router AP chips are the highest-certification-barrier link in the Wi-Fi supply chain; the significance of WQ9301 is not in its specs but in the AP side having completed the entire path from tape-out to volume shipment. Sources: WuQi Microelectronics, Sina Finance

II. Instruction Set and Architecture Ecosystem

XiangShan: Over 90 Commits in a Week, with Verification Outpacing Features

The five XiangShan repositories (XiangShan/NEMU/difftest/XSCache/GEM5) accumulated over 90 commits this week, the vast majority landing in verification and correctness rather than performance features.

  • Main repository XiangShan: On 10-26, 35 fixes were merged in a single batch, all timestamped 10-26 16:32, while the original author dates span 2026-02-04 to 09-17 — a bulk recovery of long-lived branches. Themes centered on TLB need_gpa masking and timeout clearing, guest physical address extension for vector exceptions, ignoring MXR on implicit G-stage reads under RVH, flushing the VS-stage PageCache on HFENCE.GVMA, and reset values plus X-state governance (this group accounts for a third of the batch). On 10-27, 7 more functional fixes were merged, the two most critical being in the store queue — decoupling physical-address matching from virtual-address matching (#6769) and only dequeuing a completed store-queue prefix (#6768) — targeting precisely the ordering issues where out-of-order cores are most error-prone under a weak memory model. Four more landed during the day on 10-30, including phase one of front-end instruction prefetch enhancement (#6691), MBTB allocation hiding VBTB branches (#6750), a software prefetch flow fix (#6735), and a gsim upgrade of difftest with CI lightSSS enabled (#6802).
  • NEMU: About 13 commits for the week, with the focus shifting from “adding features” to “making differential comparison trustworthy” — MMA event encoding changed to decode by mcfg semantics (#1269), host FMA exception flags faithfully propagated (#1268), FP8 MMA (#1266), AME state rollback to support replay (#1255), new NutShell and layered BOOM quick-reference configurations (#1273, #1262), and shared FAST reference reusing HostTLB (#1270).
  • difftest: About 22 commits for the week, advancing on four fronts — integration of Berkeley’s BOOM out-of-order core (#998), pushing the framework from “verifying only XiangShan” toward “verifying other cores”; support for remote XDMA board relay (#1011), removing the constraint that the verification machine and the board must be the same host, complemented by fork reference wrap-up (#1010) and FPGA-side Delta/AXI timing isolation (#1004) — in essence, pooling verification resources; continuous MMA path optimization, including a synchronous verification switch (#1009), integer saturation fix (#1008), writeback pooling reuse (#1014), operand slot prefix reuse (#1016), and physical register layout fidelity (#1013); and FST waveform output added to gsim (#867).
  • XSCache: CoupledL2’s hint arbitration changed from fixed priority to round-robin (#46, supplemented by #48 on 10-30), fixing a starvation-class defect where one hint path continuously held arbitration while another could not obtain a grant for long periods — a bug that only surfaces under prolonged stress testing.
  • GEM5: This week added an optional TEA profiling path (#1255); shortly before that, it merged an sv48 functional-level TLB initialization fix, an L2 prefetch source identification fix in CDP, and Sstc timer support.
  • Assessment: Taken together — the 35-commit bulk recovery, the 7 store-subsystem fixes, and difftest’s resource pooling — XiangShan’s current-stage task is “clearing the books before tape-out.” Issues like X-state, reset values, and need_gpa timeouts do not affect functional demos; they only surface under long-running, multi-core, and virtualization stress.
  • Sources: XiangShan, NEMU, difftest, XSCache #46

CORE-V: Patching Edge Cases Like CBO That “Never Trigger Until They Corrupt Data”

  • Two cache block operation (CBO) fixes (10-28): Stall an uncached cbo.zero through its final beat keeps cbo.zero on non-cached regions stalled through the final beat, preventing pipeline release before the write response completes; Send cbo.clean/flush/inval to the D$ through PBMT=NC/IO aliases ensures all three operations still reach the data cache correctly when the page table entry is marked non-cached or as an IO alias (PR #2010, #2008). CBO is the most easily overlooked group of instructions in RVA23 — it does not show up on performance leaderboards like vector extensions do — but both of these are data-integrity issues.
  • License and documentation cleanup (10-29): PR #1950 is a comment-only change, deleting 3,868 lines with no additions, keeping only the SPDX identifier in each file; the review record also flagged two to-dos — the 9 test files that entered main after branch creation still carry full license blocks and must be trimmed after first merging main, and this change conflicts with #1954 (cleaning src header files) and #1952 (cleaning comments and removing unused modules), so merge order must be agreed upon. Separately, #2014 adds the total SRAM macro capacity of the gc-series configurations to the README.
  • Sources: cvw commit log, cvw #1950

DAMO XuanTie: 13 Commits in a Single Day on torq-tile, Systematizing GEMM for RVV and Ztt Extensions (Backfilled This Week)

This item was not covered in the daily report for the period (the organizational-level check in the 10-29 daily judged XuanTie to have “no pushes within the window”); this weekly report backfills it after reviewing the commit log: the XUANTIE-RV torq-tile repository saw 13 consecutive commits between 10-28 11:03 and 12:56, all by author ms-shao, constituting a systematic round of completion.

  • Three-layer expansion of the GEMM mainline: Added Ztt floating-point GEMM, Ztt Q4_K and extended Q6_K GEMM (low-bit quantized matrix multiplication), plus RVV FP32 W4A16 and INT8 W2A8 output paths and an RVV FP32-bias variant; on the performance side, improved RVV low-bit decoding and accumulation.
  • Correctness fixes: Fixed RVV zero-point and requantization behavior, the dwconv depth-multiplier channel order, and NaN preservation in conv on unbounded floating-point paths.
  • Engineering boundaries: Added freestanding kernel support (no dependency on a host runtime), introduced ISA isolation and relocatable installation, and decoupled RVV geometry parameters from common header dependencies.
  • Documentation and benchmarks: Completed open-source documentation for RVV and Ztt, and filled in public benchmark and reference implementation support.
  • Observation: The shape of these commits is noteworthy — the same author delivered operators, quantization semantics, build isolation, and documentation together on the same day, indicating this line has passed the prototype stage and is being closed out to a “publishable” standard. Ztt and RVV providing low-bit GEMM in parallel points to the same thing: in real on-device and edge inference workloads, quantized matrix multiplication such as W4A16 and W2A8 offers better cost-performance than high-precision GEMM.
  • Source: torq-tile commit log

Compilers and Toolchains: LLVM 23 Lands, Triton Backend Tracks Upstream, Language VM Adds RISC-V JIT

  • openRuyi adds llvm23 (10-30): The distribution packages it separately as SPECS: Add llvm23 with version 23.1.4, coexisting with the existing clang-wrap (updated daily through 20261030 this week). The practical implication for RISC-V users is that, for the first time, the distribution allows selecting the LLVM 23 toolchain on a side-by-side version basis rather than being locked to a single clang version.
  • SpacemiT spine-triton (10-27 to 10-28): Upgraded the download link for prebuilt spine-mlir 0.8.1 in sync and bumped the version number; retuned the matrix-vector transpose 4D (VMT4D) example to the “benchmark-optimal” 128×32 tiling with a preprocessing transpose; the previous day fixed a RISC-V ISA-side constant capture shadowing kernel parameters. The two repositories have formed a synchronized cadence, and “the example is the benchmark” — what downstream gets is not a sample that merely runs, but a reproducible performance baseline.
  • Pharo 14 released (10-26): Among the three structural VM changes in the Smalltalk development environment, the most directly relevant to RISC-V is the new RISC-V JIT, alongside unified frame and stack management and extended memory management. The language VM is the most easily overlooked layer of the ISA ecosystem; a missing JIT backend means an entire class of developers cannot get usable performance on RISC-V.
  • RVA23: A Retrospective from “Year of Landing” to “Where It’s Stuck” (10-27): A 36Kr long-form piece cited RISC-V International CEO Andrea Gallo’s judgment that 2026 is the year RVA23 application processors land, with three inflection points occurring simultaneously over the past year (RVA23 profile landing, server platform specification 1.0 release, and high-performance chips appearing en masse). On obstacles, it offered the “last 1% to 5%” framing — more than 90% of an industry solution’s foundation is generic; what actually blocks progress is which databases and middleware finance must adapt, and which specialized toolchains industry must adapt. Three time points were given: four or five comparable players emerging by 2028, a preliminary RISC-V plus AI server ecosystem by 2030, and an ecosystem that is basically usable by 2035. Feedback from Chen Zhibiao, CEO of YashanDB at the Shenzhen Institute of Computing Sciences, was more direct: code-level adaptation and functional usability on RISC-V were completed this year, but core performance scenarios still lag considerably.
  • Sources: openRuyi commit log, spine-triton, Pharo 14, 36Kr retrospective

III. Operating Systems and Distributions

openRuyi: A week of commits almost entirely devoted to “non-architecture issues”

This week’s day-by-day content in the main openRuyi repository forms a clear sequence of gap-filling, running from application dependencies all the way to the virtualization foundation and benchmarking tools.

  • 10-26 issue (committed 10-23): 20 commits, all in the SPECS directory and all new Go packages—the gobuffalo family (packr/packd/logger/envy), emicklei go-restful, docker’s libtrust and spdystream, gopkg gorp v1, plus mymysql, go-mssqldb, pcidb, plist, civil, and others. This moves “Go toolchain usable” forward to “application dependencies complete.”
  • 10-27 issue: 46 commits, committed mainly on 10-26, with original author dates from 09-19 to 10-23. The core is [security-fixes]-tagged security updates for the cloud-native stack (nats-server 2.15.1, moby 29.9.2, etcd 3.7.2, containerd 2.4.2, fzf 0.74.5), openjdk-latest bumped to 27.0.1.0.2.1, and a full set of new Sequoia PGP components (sequoia-sq, sqv, sequoia-sop, sequoia-chameleon-gnupg, sequoia-git, sequoia-policy-config, sequoia-keystore-server, sq-cryptoki), plus 7 Rust dependency packages.
  • 10-28 issue: 20 commits, upgrading the entire Samba ecosystem to 4.25.1 and switching uniformly to the Waf build macros (with tdb 1.4.15, talloc 2.5.0, tevent 0.17.2), fixing jack2 client connections and enabling resampling, bumping cmocka to 2.0.2 with unit tests enabled, and backporting ceph fixes for ceph-volume/mgr/cephfs-mirror/rgw.
  • 10-29 issue: 20 commits, with the rust-vmm component family landing as a group (rust-linux-loader 0.14, rust-vm-memory 0.18, rust-kvm-ioctls 0.25, rust-acpi-tables bumped to 0.2.1), three krb5 service-system commits refactored together (KDC paths and systemd services aligned, realm configuration made neutral, build options switched to system libraries with upstream tests run), plus Go index optimization and build-chain maintenance for cmake/scikit-build-core/httptools/attr.
  • 10-30 issue and Friday daytime: 20 commits plus about 10, with 13 kf6-* packages synced to KDE Frameworks 6.31.0 (covering kio, kwallet, ksvg, prison, kguiaddons, threadweaver, syntax-highlighting, syndication, sonnet, solid, qqc2-desktop-style, purpose, networkmanager-qt), the new Vulkan peak-performance benchmark vkpeak (measuring vector and matrix peaks for fp32/fp16/fp64, int8 through int64, bf16, and fp8), the new llvm23 23.1.4, ollama bumped to 0.40.7 and tagged security-fixes, and clang-wrap updated to 20261030.
  • Dual-source verification conclusion: The latest announcement on the official news page is still the 2026.09 release (published September 30, improving RVA23 support, expanding the cloud and storage software stack, and upgrading the Go 1.27 build environment). The October release has not yet shipped, and there were no new release announcements this week.
  • Assessment: One main thread is clear—the main workload for RISC-V distributions right now is security debt and dependency coverage, not new features. Without fixing CVEs in components like nats, etcd, and containerd, server scenarios are out of the question; pulling in the entire Sequoia suite (including a GnuPG compatibility layer like sequoia-chameleon-gnupg) means package signing and key management must be rebuilt on a modern PGP stack; and the four rust-vmm components landing as a group shows that the dependencies for running Rust-written VMMs on RISC-V are now in place—a deeper impact than porting any single application. The significance of vkpeak entering the repo lies in the measurement baseline—Vulkan devices on RISC-V previously had no unified peak-compute comparison tool, and now they can be compared directly against x86 and Arm boards.
  • Sources: openRuyi commit history, vkpeak SPEC, openRuyi official news page

Other distributions and the kernel side: no substantive additions this week

  • RevyOS: Four repositories (opensbi, ruyiedk2, edk2, coreboot) showed second-level batch-push characteristics on 10-27; a commit-log check of the main branch found no new commits within the window, so this is judged to be branch or mirror synchronization rather than development (the 10-28 issue corrected the previous day’s misjudgment on this); the 10-30 issue recheck found zero commits for revyos’s linux and edk2-platforms.
  • openEuler: None of this week’s five daily reports contained a RISC-V item eligible for inclusion, and there was no public activity within the window on the official site or the code-hosting side, so this report does not cover it separately.
  • Linux kernel: None of this week’s in-window items from Phoronix, LWN, or LinuxGizmos were RISC-V-specific (they focused respectively on Linux 7.4 subsystems and NVIDIA/AMD drivers, scheduler and container topics, and Jetson carrier boards); the RISC-V landing points in 7.3 were recorded in the previous weekly report and are not repeated here.
  • Assessment: The dense activity on the distribution side is concentrated in openRuyi alone, while other distributions are in a synchronization and maintenance rhythm. This is consistent with the timing of the summit having just ended and resources shifting toward delivery, and it also means that, in the near term, observable progress in the RISC-V server software stack will mainly be tracked through openRuyi’s commit curve.

IV. Chips and Hardware

IP Layer: Within One Week, Three Companies Give Different Versions of the Same Answer

  • Codasip sells off low-end cores, pivots to CHERI (10-26): For $14.5 million, it hands its low-end RISC-V processor business and 27-person team to onsemi, while retaining ownership of its Studio tools and pivoting to a CHERI-based “cyber-resilient” security architecture. The CHERI direction already has a direct rival in SCI Semiconductor, which completed a £5 million funding round in September 2026 and claims an additional £7.7 million in government contracts; Codasip CEO Ron Black told the CHERI Alliance that security requirements from defense and critical-infrastructure customers are stronger than demand for general-purpose core licensing.
  • SiFive turns cores into an “accelerator control unit” (10-26 to 10-28): Using its Intelligence series, it inserts a programmable control plane between the host and custom accelerators, handling low-latency command dispatch, data movement, pre/post-processing, and algorithm tuning, connecting directly to accelerators via coprocessor interfaces such as SSCI and VCIX; the X100 targets control-intensive and low-latency scenarios, while the X200/X300 offer greater vector bandwidth. Two pieces of confirmed information: Google data centers already use the X200 as an AI compute host, and the X100 has been licensed to an unnamed top-tier U.S. semiconductor company for industrial edge AI. SiFive’s own framing is that “value is moving out of the ISA.”
  • MIPS’s three platforms after dropping its own ISA (10-26): Acies-1 (inference-native, based on Atlas S8200, supporting RVA23, RVV, and VME, capable of running llama.cpp, Qwen, vision Transformers, and VLAs, in an M.2 PCIe form factor); Actus-1 (event-native, based on Atlas M8500, with real-time multithreading plus FoC acceleration, integrating a VPX vector coprocessor, compliant with ISO 26262 and ISO 21434); Aegis-1 (security-native, targeting mission-critical physical AI). The S8200 integrates scalar, vector, and matrix engines, with the company claiming 4x higher TOPS/W energy efficiency than current products; it has shipped samples to key customers, with the first silicon reference platforms expected in 2027; customers cover nine of the world’s top twelve automakers.
  • Assessment: Three companies gave different answers to the same conclusion in the same week—general-purpose core licensing is depreciating, and what matters is whether you can embed into the customer’s system architecture. The implication for domestic vendors is direct: rather than directly replacing Arm host controllers, it is better to build control and scheduling layers alongside AI accelerators—a path with far lower software-ecosystem requirements and one that is easier to win orders with first.

Automotive-Grade, Security, and Aerospace: The Three Areas with the Densest Hard Metrics This Week

  • ESWIN (10-28): The R520A passed TÜV Rheinland ASIL-D certification, becoming the world’s first multi-core, multi-architecture RISC-V core to achieve ASIL-D; the EAM2011 automotive-grade MCU has entered mass production for display assemblies, in-car wireless charging, and BMS; and its consumer AI NAS with JiKong is scheduled for mass production in Q4 2026. The most solid line from the interview is that the automotive barrier is not in the chip but in the system—from supply chain to Tier 1 to automaker adoption, the chain is extremely long, and building the chip is only the first step; the key to ASIL-D is that it turns “can it get into the ADAS domain” from a business question into a certificate question.
  • SpacemiT K3 security documentation becomes systematic (10-26): The documentation repo adds 10 commits in one batch to the security documentation master index, security whitepaper, and feature support matrix, plus the TEE architecture and image guide, TA/CA development guide and examples, TEE debugging guide, key management, secure storage, and “firmware layout after introducing TEE.” Once TEE enters the firmware layout, key injection, debug port policy, and the OTA trust chain in mass production all change accordingly; releasing this batch of documentation at once indicates that K3’s secure boot and trusted execution environment have entered the external delivery stage.
  • Sophgo SG2044 firmware fills in the delivery chain (10-26): The EDK2 firmware repo has 6 commits on the devel-sg2044 branch, all authored the same day—adding SOPHGO’s default RSA signing key and a firmware binary signing script, a firmware.bin packaging tool, an envsetup.sh that supports working outside the full EDK2 tree, and bringing all SG2044 platforms into CI builds. Following the 10-08 release of BIOS v2.1.1 and the 10-23 refactor of the bootloader repo zsbl to the eboot framework (supporting out-of-tree application trees and external device trees), these commits precisely fill the delivery-side gap left after the refactor. The long-standing weakness of domestic high-performance RISC-V servers has never been the core, but “whether the firmware can be safely flashed by customers.”
  • Microchip PIC64-HPSC early irradiation results (released 10-27, reported 10-28): Early characterization of the radiation-tolerant PIC64-HPSC1000-RH shows total ionizing dose TID reaching 200 krad(Si), single-event latchup SEL tested to 78.2 MeV·cm²/mg, and no uncorrectable errors in the system controller during single-event effect characterization, with no external reset required. The series originated from NASA and JPL’s assessment of space computing needs, awarded to Microchip in 2022; the early access program has provided silicon and development kits to customers, and board partners are developing VPX and VNX+ compute modules. The 200 krad(Si) level means mission coverage can range from LEO to beyond the Moon, and the SEL and SEE data are the entry ticket for space-grade selection.

Edge Devices and Development Boards: The Only Direction with Real New Product Launches This Week

  • LILYGO T-Display K230 (10-28): A handheld development kit powered by the Canaan Kendryte K230 dual-core 64-bit RISC-V (1.6GHz big core with RVV 1.0 and FPU, 800MHz little core supporting RV64GCB), with a built-in KPU supporting INT8/INT16 (official typical network performance: ResNet50 at no less than 85fps, MobileNetV2 at no less than 670fps, YOLOv5S at no less than 38fps) and H.264/H.265 hardware encode/decode. The device features a 4.1-inch 568×123 AMOLED, 1GB LPDDR4, a 2MP camera, HDMI 1080p30, 100M Ethernet, WiFi 4, and SX1262 or LR2021 LoRa; an optional keyboard dock adds an nRF9151 supporting LTE-M/NB-IoT/GNSS. The bare board is about $98.79, and the kit about $150. The K230 is one of the few domestic RISC-V dual-cores that “can run Linux and has a built-in KPU”; packaged as a handheld with a physical keyboard, its positioning is clear—LoRa and Meshtastic-style mesh networking scenarios previously had only Raspberry Pi solutions or pure MCU solutions, neither of which fit well.
  • Adafruit Metro ESP32-P4 Hydra (10-26): Puts the ESP32-P4 into an Arduino UNO form factor and adds an ESP32-C6 for wireless. Dual-core 32-bit RISC-V at up to 360MHz (with AI instruction extensions and single-precision FPU) plus a 40MHz low-power core, 16MB PSRAM, 16MB QSPI NOR, Raspberry Pi-compatible 2-lane MIPI DSI and CSI, a USB 2.0 high-speed OTG host port, microSD, and UNO headers. The UNO form factor means existing expansion board inventory can be reused directly; this kind of engineering convenience often drives selection more than a few extra tens of megahertz.
  • GUITION VisionGo series (10-28): The flagship is the 7-inch ESP32-P4 all-in-one display JC1060P470C_I_W_Y—dual-core RISC-V at the 360 to 400MHz level, 1024×600 IPS capacitive touch, 32MB PSRAM, 16MB Flash, integrated WiFi and Bluetooth, with some models supporting MIPI-CSI; the full series covers 1.28 to 21.5 inches and is compatible with ESP-IDF, Arduino IDE, MicroPython, LVGL, ESPHome, and Home Assistant. The ESP32-P4 is solidifying “HMI screen plus host controller” into a standard module form factor; for teams building smart home panels, energy-storage inverter human-machine interfaces, and charging pile displays, the hardware barrier is reduced to “pick a screen and write the UI,” which also means hardware margins in mid-to-low-end HMI will be eroded faster.
  • Keybytes modular keyboard (10-26): Each key is an independent 1u circuit board, each with a CH32V003-series RISC-V microcontroller, with pogo pins on all four sides carrying power and I2C, keys attached magnetically and rearrangeable into any layout; the entire keyboard needs only one aggregation module. A single key board costs about $2, the aggregation module about $30, and a full-size unit’s materials and assembly about $900. Conventional keyboards use one chip to scan the entire matrix; Keybytes instead distributes scanning capability to each key—it has no cost advantage, but for devices that need frequent layout changes, such as one-handed keyboards, accessible input, and split ergonomic designs, it is a genuinely viable path.
  • Mijia Desktop Water Purifier 3 (10-27): Priced at 1,499 yuan, it uses a RISC-V chip combined with patented slow-release technology to steadily release six minerals including strontium, zinc, and calcium into the water (measured strontium content no less than 0.2mg/L), and on that basis dynamically extends RO filter life to 3 years. This is a rare case of RISC-V in home appliances “carrying control algorithms rather than just acting as a switch”—mineral slow release and dynamic filter-life calculation both require sensor closed loops and model computation, which are control-type workloads, a low-profile but real path for replacing Cortex-M.
  • Domestic Compute: Two Deployment Samples of GPGPU and Super Nodes
  • Youzhi Chuangxin (10-22, Monday issue window): The Tsinghua-affiliated brain-inspired intelligence company completed a nearly 100 million yuan Pre-A round, led by Liyou Venture Capital, a special fund formed by Lihui Fund together with Changsha Investment Holdings Group and Jinxia Shengshi Fund, with existing shareholder Qifu Capital following on; at the same time, it is landing its incubated “Quanyingxin” RISC-V GPGPU project in the Changsha Jinxia Economic Development Zone. The technology traces back to “Ventus (Chengying),” China’s first open-source RISC-V vector-extension GPGPU, launched by the Shanghai Tsinghua International Innovation Center in 2022, with a route of triple independence in instruction set, architecture, and ecosystem. In June 2025, the project with total investment of about 1.5 billion yuan was signed and settled, to be built in three phases, with annual output value after the first phase expected to exceed 300 million yuan; at the operator library level, Changsha Quanying Semiconductor and others signed a strategic cooperation agreement on OpenCL operator libraries with CSDN, Jingjia Micro, and Changsha Shouzhua Technology, aiming to resolve ecosystem fragmentation in operator adaptation. A GPGPU on RISC-V means building a complete parallel programming stack from scratch; whether the joint OpenCL operator library effort can produce genuinely reusable code is the most worthwhile metric to track going forward.
  • Epoch (10-23, Monday issue window): At the XiangShan Ruyi Ecosystem Conference, it became one of the eight inaugural members of the open-source chip community’s RVAI Working Group and a co-builder of the Ruyi community. Its first-generation Epoch series RISC-V cloud AI chips have entered large-scale mass production, natively supporting block-wise quantized FP8; a 64-node E200-L liquid-cooled OAM super-node cluster has gone live in a carrier data center, which the company claims is the industry’s first mass-delivered RISC-V super node, achieving 100-nanosecond-level interconnect across 64 chips, used for expert routing coordination in MoE models. In the first half of 2026, it completed a 1.5 billion yuan B round and received strategic investment from China Mobile, and in September raised nearly 2 billion yuan more, at a post-money valuation approaching 15 billion yuan; on the software side, it is advancing the open-sourcing of the VISA virtual instruction set, and its EVACA software stack has been adapted to domestic AI ecosystems such as FlagOS.
  • Sophgo model adaptation shifts to sparse large models (10-28 to 10-30): LLM-TPU added a download link for the qwen3.6-35b-a3b bmodel; the prior cadence was Python examples for MiniCPM5-2B and MiniCPMV4.7, and compatibility support for bge-reranker-v2-m3 and MinerU2.5-Pro; on 10-30 it also merged InternVL3 and Qwen3-ASR fixes (feeding token ids rather than raw logits into embed_cache). 35B-A3B is a sparse MoE model with only about 3B active parameters; being able to offer it as a downloadable bmodel on the TPU shows that adaptation has moved from dense small models to sparse large models—such models are more sensitive to memory bandwidth and scheduling and less demanding on peak compute, which is exactly the comfort zone of domestic TPUs.
  • To watch: SpacemiT’s docs-product adds CoM260 module MCU firmware flashing resources (10-29), a matter of improving product delivery documentation; ESWIN’s AI NAS Q4 mass production is a verifiable time point worth revisiting next quarter.

V. Open-Source Community and Industry Activities

Robotics Software Stack: Expanding from “Runs on Our Own Model” to “Runs on Others’ Models Too”

  • Third-party model adaptation (10-26): SpacemiT’s spacemit-robotics added the unitree-go2 repository, titled “Go2 on SpacemiT K3.” The README directly provides a startup script to run as root on the K3 board (the SDK resides in an agreed-upon directory on the device and uses the new_bigcore configuration), and specifies that Pose A (the crouch pose) must be set before startup and set before power-on for auto-start. A companion web console is accessible from the same subnet. The 5 commits in the window include a ROS 2 application plus ONNX policy plus web control, along with simplified SDK delivery, camera frame synchronization, and hardened CI model downloads.
  • Humanoid side (Linglong L1 V1.4): 28 degrees of freedom (6 left leg + 6 right leg + 2 head + 7 left arm + 7 right arm), supporting MuJoCo simulation and whole-body real-machine backend switching, sim2sim cross-machine inference (PC simulation plus K3 board-side RL inference), K3 real-machine 28-axis motor and parallel ankle / Forsense IMU control, plus an Android App and a QR-code web page connected via the HMI service.
  • Middleware layer (10-28, 10 commits): humanoid_common integrates a motion adapter and operator client, connecting capabilities such as motion and voice to the body runtime as remote services; control_whole_body supports tabular joint coupling and feedback recovery; unitree-go2 switches to a V2 walking policy that is “terrain-only” and pins model downloads to a specified version, and IMU snapshot reads no longer copy motor state along with them; peripherals-imu supports HI91 serial feedback and reuses the BMI270 kernel IIO channel, throttling reads; realtime-link adds video transmission, providing a single-header C ABI and a board-side frame-capture example based on the MPP codec.
  • Reading the cadence: On 10-27, 8 repositories were pushed in the same second with no new commits on the main branch, judged to be branch or mirror synchronization; on 10-28, 10 substantive commits landed across four repositories; on 10-29, it returned to zero commits. The method for reading this column should stick to examining main-branch commit content, with conclusions following the evidence. Replicable model adaptation is worth more than a single-machine demo — existing quadruped robots like the Go2 are numerous and have relatively open SDKs, so using one as an external showcase for the K3 demonstrates platform capability better than tuning yet another version of the humanoid.

Conferences and Community: Open-Source Tapeout Adds DFT, Chiplet Interoperability Gets an Open-Source Scaffold

  • RISC-V Day Tokyo 2026 Autumn (11-11, University of Tokyo Hongo Campus) agenda published: One 30-minute talk presents a complete path to tapeout using a purely open-source toolchain — the speaker used LibreLane 3.1.0.dev2 to push the self-developed RV32I-compatible core SWC1 to GF180, with the flow covering Verilator lint, Yosys synthesis, OpenROAD place/CTS/route, 9 signoff STA corners, dual DRC with Magic and KLayout, and netgen LVS, for a total of 78 process steps. What is new this time is DFT: two steps are inserted after synthesis — scan FF replacement and scan chain creation — using the open-source ATPG Atalanta to generate 14,148 test patterns in about 2 minutes with 97% fault coverage; after scan chain insertion, frequency drops from 50MHz to 19MHz. The pitfall log is equally concrete — the public 5V SRAM template passed, but swapping in their own core failed repeatedly, and it turned out they had built a 3.3V core from 5V cells. The technical significance is not the conclusion “tapeout with open-source tools” (Tiny Tapeout proved that long ago), but adding DFT into the open-source flow: scan chains and ATPG have long been commercial EDA territory, and a hobbyist achieving 97% fault coverage on WSL2 shows that the open-source flow’s weak spot is shifting from “can it tape out” to “can it be made testable.” The next talk in the same session is “AI-Designed RISC-V: From Claude Code to Linux Boot.”
  • Tenstorrent opens OCA Harness beta (10-23, Monday-window issue): Open Chiplet Atlas Harness turns the chiplet interoperability architecture into a reusable implementation, with code under Apache 2.0 and documentation under CC-BY-4.0, targeting a formal release in January 2027; the three-layer structure is Architecture (five layers of interoperability: physical, transport, protocol, system, software), Harness (all the “non-application logic” a chiplet needs), and Compliance (pre-silicon verification and post-silicon validation). The real obstacle for chiplets has never been whether they can be built, but that each vendor’s die-to-die interface does not recognize the others’; making non-application logic into an open-source scaffold essentially moves the interoperability cost from each design team to the community.
  • Tenstorrent and Vayavya Labs’ virtual platform partnership enters localized coverage (10-29): Vayavya used its TvastaaVP to build a SystemC virtual platform for Tenstorrent’s security and system management IP, letting software development and validation begin before silicon is available; the 10-29 Indian media report adds two incremental points — this line started as a one-off modeling effort in 2024 and later evolved into a multi-year agreement, and Vayavya is using the partnership to strengthen its position in India’s semiconductor ecosystem.
  • Industry judgments and personnel (10-23 to 10-30): In an interview, Wu Xiaozhong, Vice President of UniVista (合见工软), offered a “watershed” judgment on RISC-V — the Arm era was “architecture standardized first, tool adaptation after,” while the RISC-V era has become a symbiotic model with architecture, IP, and tools advancing in parallel; the company has already invested simulation and hardware emulation capabilities in real R&D projects on XiangShan Kunminghu and the XuanTie C900 series, and believes the real difficulty of verification is not inventing new methodologies but the workload of configuration management and hardware-software co-design. Summit chair and Ruisilicon (睿思芯科) founder Tan Zhangxi, meanwhile, predicts a shakeout among the twenty to thirty companies claiming to do high-performance RISC-V, and that ecosystem building matters even more than chasing core performance. On 10-30, another report said that Chen Mingxiu, head of DAMO Academy’s Leyun embodied intelligence platform, has left and founded Muling Technology in Yuhang, Hangzhou, focused on Physical RSI; this is the third core personnel change at DAMO Academy within two months, and as a personnel move in the embodied team it has no direct technical connection to the RISC-V instruction set or XuanTie IP.
  • Sources: RISC-V Association (Japan) agenda, tt-oca-harness, Tenstorrent newsroom, SEMI China semiconductor industry site, 21st Century Business Herald (Tan Zhangxi)

RISC-V 100 Leaderboard Weekly Update

This week riscv100.top showed no significant changes. The 10-28 archive and the 10-29 and 10-30 inspection rounds all reported “no changes,” and the 10-31 recheck produced consistent results: What’s New still has two entries (OpenXiangShan KMHv3 RTL XSCC 2.0 SPEC CPU2006 Speed, SpacemiT K3 X100 version progress), Upcoming still has three items (AWS Graviton5 Neoverse V3, SpacemiT K3 X100 vectorization and IME, GCC 16 SPEC CPU testing), the committee still has 11 members (BenchCouncil 2, Academia 4, open-source organizations 2, industry 3, with the open-source organization seats including one each from the XiangShan compiler team and OpenXiangShan), and the six SPEC leaderboards have no new records or numerical changes. The most recent record remains the 10-15 cross-architecture and RISC-V dual leaderboard SPEC CPU2006: the XiangShan compiler team’s XSCC 2.0 on XiangShan KMHv3 RTL at 3GHz scored int 67.85 and fp 76.54 (speed/ref, Completed), an improvement of 2.1% in int and 6.1% in fp over the same compiler’s previous record (10-07). Source: riscv100.top

VI. Trend Watch

  • The valuation center of general-purpose core IP has shifted to transaction prices: Codasip’s low-end RISC-V business changed hands for $14.5 million with 27 people, while SiFive is selling “accelerator control units” and MIPS is doing “workload-native” platform tiering. Three companies give different versions of the same conclusion—basic cores are hard to differentiate, and only the layer that can be embedded into a customer’s system architecture is valuable. For domestic vendors, this judgment is more direct than any roadmap: building control and scheduling alongside AI accelerators is easier to win orders with first than directly replacing the main controller.
  • Verification has become the main battlefield of open-source core competition, and the focus is shifting from throughput to semantics and resources: In a week of XiangShan difftest commits, there are throughput optimizations such as Tensor Cores running INT8 comparisons and CUDA pipelining, resource pooling such as remote XDMA relay and fork reference cleanup, and precision semantics fixes such as floating-point exception flags, integer saturation, and FP8 accumulation. Together, the three show one thing—the cores being verified are already too complex for pure software simulation to keep up, and with FP8 in the picture, precision-semantics consistency matters more to success than throughput. In the same week, CORE-V added CBO’s non-cache last beat and PBMT aliasing, which belong to the same category of boundaries that “usually don’t trigger, but corrupt data once they do.”
  • The bottleneck for distributions has shifted from “whether packages exist” to “whether they can go into production”: openRuyi had about 130 commits in a week, mainly security fixes, PGP and key systems, the rust-vmm virtualization base, measurement tools, and build macro migration, rather than new application ports. Security updates have begun to go through the process in batches with the [security-fixes] tag, indicating they have entered a processized channel; the official website version is still at 2026.09, and the commit cadence and release cadence are not synchronized. This “fast rolling maintenance, slow version releases” pattern is expected to continue until the October release.
  • What domestic teams filled in this week is all the last mile before delivery: Sophgo’s firmware signing keys, packaging tools, independent build environment, and full-platform CI; SpacemiT’s TEE white paper, TA/CA guide, and debugging documentation; Nuclei’s QEMU NICE, XEC extensions, and trace decoder documentation; SpacemiT’s CoM260 flashing resources. None of these make it into a launch event, yet they determine whether the next batch of systems can ship—more meaningful than another version of the spec sheet.
  • The device side remains the only landing point with real shipments, and its forms are standardizing: WQ9301 has completed the full AP-side mass-production process, ESP32-P4 has been made into two standard forms—an UNO and a 7-inch all-in-one screen—K230 has entered a handheld kit with a keyboard, RISC-V handles the control algorithm of a water purifier, and CH32V003 supports a keyboard with one MCU per key. The common thread is cheap chips, closed-loop algorithms, and volume on the consumer side, in contrast to the server side, where performance is still being argued.
  • The RISC-V entry point for embodied intelligence remains the “cerebellum” and communication control, and suppliers are starting to build platforms: The route given by ZeroErr Robotics is to keep the mature application host and first introduce RISC-V in the communication and control links, because these positions have clear responsibilities and interfaces, and the benefits can be proven quickly; SpacemiT, meanwhile, has expanded its robot stack from its own Linglong to third-party models such as Unitree Go2, and added voice and video transmission. Industry data points the same way: the RISC-V penetration rate in China’s embodied intelligence chip market is 10.7% in 2025 and is expected to be 28.2% in 2030, while the main control chip market grew about 34 times in four years—the increment mainly comes from general-purpose main controllers and the consumer side, and the high-compute chips on the robot body itself remain Arm’s and x86’s territory.
  • Security-related custom instructions become a new landing point: A post-quantum paper provides a checkable selection map (which sub-operations yield the highest benefit per unit of logic, and which are only worth it when keys are generated on that device), ESWIN turns an ASIL-D certificate into a ticket into the intelligent-driving domain, and SpacemiT writes TEE into the firmware layout. What the three have in common is that RISC-V’s extensibility is shifting from “performance customization” to “compliance and security customization,” and the latter has higher procurement certainty.

Appendix: Sources and Verification Notes

Source Composition

  • Five daily briefings: 2026-10-26 (72-hour window, covering 10-23 05:00 to 10-26 05:00), 10-27, 10-28, 10-29, and 10-30 (each a 24-hour window continuing from the previous cutoff). The main body of this report therefore covers events across the eight days from 10-23 to 10-30; the period from daytime 10-23 to 10-25 falls within the normal coverage of the Monday edition, and the affected items are labeled with their original dates in the headings.
  • Friday fill-in: the final cutoff of the five daily briefings was 10-30 05:00, so activity during daytime 10-30 falls outside all daily windows. This report separately re-checks that period; items written into the main text include: 4 commits in the XiangShan main repo (#6691 front-end instruction prefetch phase 1, #6750 MBTB allocation, #6735 software prefetch flow, #6802 gsim upgrade), 1 in NEMU (#1255 AME state rollback), 2 in difftest (#1016 operand slot reuse, #1004 Delta and AXI timing isolation), 1 in XSCache (#48), and about 10 in openRuyi (llvm23 23.1.4, ollama 0.40.7, clang-wrap 20261030, and three Go packages), all verified commit-by-commit via commits.atom.
  • This week’s backfill: 13 commits in DAMO XuanTie torq-tile during daytime 10-28 were not covered by the daily briefing for that period (the organization-level check in the 10-29 briefing judged there were no pushes, which was in fact a missed detection caused by API rate limits). After re-checking the commit stream, they have been added to Chapter 2 and recorded in the table below.

Supplementary Verification Results

Check Item Result
GitHub watched organizations (168-hour window) The organization-level anonymous API was rate-limited for most of the week, returning rate limit per organization; switched to checking each key repository’s commits.atom individually. Commit lists within the window were obtained for the five XiangShan repos, openRuyi, CORE-V, XuanTie torq-tile, SpacemiT spine-triton, and Sophgo sophgo-edk2 and LLM-TPU; organizations such as espressif, sipeed, revyos, and radxa-linkr could not be expanded repo by repo, so in-window activity in their non-key repositories may be missing
XiangShan per-repo re-check Main repo kunminghu-v3: about 56 commits this week (including the 35-commit batch recovery on 10-26 and 4 during daytime 10-30); NEMU: about 13; difftest: about 22; XSCache: 2 (#46, #48); GEM5: 1 (TEA profiling). GEM5 and llvm-project have no new commits after 10-29
openRuyi dual-source Main repo: 20/46/20/20/20 commits across the five weekdays plus about 10 during daytime Friday, roughly 130 in total; the latest release on the official news page remains 2026.09 (released 9-30), the October version has not been released, and there were no new version announcements this week
DAMO XuanTie, ESWIN, Nuclei XuanTie torq-tile: 13 commits during daytime 10-28 (this week’s backfill); opensbi, zero_stage_boot, qemu, CubeSandbox, llvm-project, gcc, riscv-aosp, and xuantie-yocto had no commits in the window; ESWIN linux-sdk and riscv-matrix-gemm-vectors had no commits; Nuclei nuclei-sdk had no commits, while the docs repo nuclei-tool-guide had 7 commits on 10-26 (QEMU NICE, XEC, trace decoder)
SpacemiT spacemit-com and spacemit-robotics spacemit-com: docs-buildroot 10 commits (K3 security documentation system), spine-triton 9, docs-product 2, plus several in the mpp and ai-sdk submodules; spacemit-robotics: 9 commits across five repos on 10-26, 10 across four repos on 10-28, zero commits on 10-27 and 10-29; the same-second pushes across eight repos on 10-27 were judged to be branch or mirror synchronization
Sophgo, Sipeed, revyos, Radxa Linkr Sophgo: sophgo-edk2 6 commits, zsbl 8 (10-23, eboot refactor), LLM-TPU 4, sophon-demo 1; Sipeed: SLogic 4 (USB transfer scheduling), SLogicWeb 1; revyos: four repos synchronized in second-level batches, no new commits on the main branch; Radxa Linkr: linkrd newly created with its first commit, all others zero commits
CORE-V and OpenHW CVW: two CBO fixes (#2010, #2008), SPDX trimming (#1950), README gc configuration (#2014); CVA6’s master became read-only on 10-23, with no commits in the window
openRuyi official news page Fetched successfully; latest announcement is the 2026.09 version, with no sign of an October release
riscv100.top inspection No significant changes this week: the 10-28 archive matches the 10-29 and 10-30 inspections; the 10-31 re-check found no changes to the two What’s New items, three Upcoming items, 11 committee members, or the six leaderboards
Member company website inspection (391 companies) Results by period: 10-26 — 277 unchanged, 45 changed, 69 fetch failures; 10-29 — changes mainly homepage refreshes at universities and research institutes; 10-30 — 219 unchanged, 105 changed, 67 failed. Within the period, only the RISC-V Association (Japan) meeting agenda constituted substantive information; no product, funding, or architecture announcements were detected otherwise
riscv.org official blog No new articles in the window; latest remain the 10-20 SoCMake feature and the 10-15 interview with Meng Jianyi of DAMO Academy
Pending-inclusion queue No pending items on this topic during the period (the 10-22 queue file contained only sections on other topics and was skipped per the rules)

Limitations and Scope Notes

  • Single source for transaction and valuation data: the price, headcount, and payment ratio of the onsemi acquisition of Codasip come from reporting by Czech media e15 and a paraphrase by Jon Peddie Research; neither company has disclosed the transaction terms. Codasip’s public funding figures are cited on its own terms. ESWIN’s “industry’s first mass-produced and delivered RISC-V supernode” and “post-investment valuation approaching RMB 15 billion” are company and media claims, not corroborated by financial statements; Youzhi Chuangxin’s funding amount, output value, and compute figures are per Changsha Evening News reporting.
  • Vendor claims not third-party verified: Wuqi Micro’s “cumulative 600 million RISC-V cores” and “WQ9301 is one of the very few mass-produced RISC-V Wi-Fi 6 APs in China” are official claims; MIPS’s S8200 efficiency multiple, the 2027 silicon reference platform timeline, and “nine of the top twelve automakers” are company claims; Microchip’s irradiation data are early characterization results, not full-parameter qualification conclusions; Ruixin D35’s “12nm surpassing NVIDIA 7nm” is 9-23 content recirculating and is not re-included this week.
  • Boundaries of research projects: Qwenputer is a personal research project that has not undergone peer review; its “18 million instructions run freely without error” is the author’s own account, and the 18.8 GB checkpoint and dedicated driver make it a research apparatus rather than a chip substitute. In the post-quantum paper, because controlbits remain on the software side, the key generation path only gives a lower bound of over 60 seconds; production parameters and side-channel resistance were not evaluated, and the scaling analysis from SD card (toy-level) parameters to mceliece348864 shows insufficient storage on the target device.
  • Date semantics of XiangShan commits: the 35 commits on 10-26 and the multiple openRuyi batches are long-lived branch batch recoveries, with uniform commit timestamps while original author dates span several months; this report notes this separately in the main text and does not count them as new development work of that day.
  • Events not yet held: the LibreLane talk at RISC-V Day Tokyo is scheduled for 11-11; the process step count, ATPG pattern count, and coverage come from the talk abstract and have not been verified on site.
  • Items not directly related to RISC-V: the departure of DAMO Academy’s Chen Mingxiu to found a startup is a personnel development in the embodied AI team; the main text explicitly notes that it has no direct technical connection to the instruction set or XuanTie IP, and it is included because the main domestic suppliers of RISC-V robotics software stacks have cooperative relationships with such teams.
  • Deduplication: items already included last week — V100, E908A, Tenstorrent’s E round, Ruixin D35, LILYGO T-Halow P4, CVA6 master going read-only, etc. — were not counted again when recirculated this week; the newly included 10-23 daytime items this week (Claude formal verification, ESWIN, Hejian Gongruan, the Tan Zhangxi interview, Sophgo eboot, SpacemiT Agent memory subsystem, Tenstorrent OCA Harness) all fall after the cutoff of the previous weekly report and do not constitute duplication.
  • Sources: all items are drawn from the daily RISC-V Global Dynamics briefings (2026-10-26 to 2026-10-30); key data were re-verified through this period’s GitHub commit streams, the openRuyi official news page, riscv100.top, and the member website inspection.