Research window: Past 24 hours (2026-09-22 07:00 ~ 2026-09-23 07:00, Beijing time). This is a regular daily window with no overlap with the previous issue. Sources: GitHub (push audit of 28 repositories in the tile-ai organization; 7 repositories had pushes within the window; main repo 1 merge and 1 new open, multiple review queue updates; TileOPs 1 merge and 5 new opens, 4 closes; TileFoundry two merges; MLIR Ascend Mamba large merge; Hygon dual-branch progress including example support PR updates; community TPU backend repo BM1690 multi-core verification; Ascend daily test workflow-level failure and A5 hardware path defect reports; nightly snapshot benchmark 1046 items zero failures, correctness 1141 items resumed publication), Google News RSS multi-group queries in Chinese and English (via proxy, zero hits), Hacker News, arXiv, third-party ecosystem repos

Index

  • Today’s Highlights: Exact FP4-to-FP8 conversion fused into main repo—DeepSeek V4.1 expert GEMM up to 5.4x faster (09-22)
  • I. Core Project Progress
    • 1.1 Main repo review queue: parallel loop fix newly opened, TileIR backend adds 8 commits (09-22)
    • 1.2 TileOPs governance wrap-up: last bypasses of manifest entries and evaluator removed (09-22)
    • 1.3 TileOPs performance sprint one: Engram decode split into projection and reduction two-stage kernels (09-22)
    • 1.4 TileOPs performance sprint two: GEMM ping-pong main loop hides dense epilogue, 176 tiles enlisted (09-22)
    • 1.5 TileOPs performance sprint three: GLA inference operators enlisted, MoE over-routing grouping (09-22)
    • 1.6 TileOPs: roofline synthesis failures become reportable, three queue updates (09-22)
    • 1.7 TileFoundry: memory metadata and traffic normalization two merges (09-22)
    • 1.8 Nightly snapshot: benchmark 1046 items zero failures, correctness 1141 items resumed publication (09-23)
  • II. Multi-Backend Adaptation (Ascend / Hygon / MetaX / Moore Threads, etc.)
    • 2.1 Ascend: daily tests reproduce workflow-level failure, three new defect tickets point to A5 hardware path and auto-sync (09-22 to 09-23)
    • 2.2 MLIR Ascend: Mamba SSD chunk scan operator large merge, tuning and integration processes refined simultaneously (09-22)
    • 2.3 Hygon: FP32 MMAC K commit extension redone; example support PR adds 32 files (09-22)
    • 2.4 MetaX and Moore Threads: no pushes within window (09-23 audit)
    • 2.5 Community backends: TileLang-TPU advances Sophgo BM1690 multi-core verification and performance matrix (09-22)
  • III. Ecosystem and Adopters
    • 3.1 Adopters: TileKernels and FlashQLA no pushes within window (09-23 audit)
    • 3.2 Community projects: MetaX C500 multi-paradigm operator development bootcamp materials continue to be submitted (09-22)
  • IV. Community, Tutorials and Events
    • 4.1 Documentation site: TileOPs documentation site one versioned deployment (09-22)
    • 4.2 Media and academia: Google News zero hits, arXiv no new papers (09-23 audit)
    • 4.3 Release cadence: no new releases, main repo v0.1.14 now 21 days old (09-23)
  • V. Trend Observations
    • 5.1 Conversion operators become first-class citizens
    • 5.2 TileOPs shifts from governance season to performance season
    • 5.3 Ascend’s alternating red and green and the real hardware test of A5
    • 5.4 Gaps and risk points
  • Appendix: Materials and verification notes

Today’s Highlights: Exact FP4-to-FP8 conversion fused into main repo—DeepSeek V4.1 expert GEMM up to 5.4x faster

Date: 2026-09-22　Source: tilelang #3204

Merged at 19:36 (opened 09-11, 11 days of refinement). The starting point of this ledger entry is a seemingly unremarkable conversion chain: DeepSeek V4.1’s expert GEMM, on every K tile, must convert E2M1 (FP4) weights through an FP32 intermediate into E4M3 (FP8). The author noticed an encoding fact—all values of E2M1, including signed zero, have exact corresponding encodings in E4M3, so this default projection chain of “expand to FP32 then compress” need not pass through FP32 at all.

In implementation, this unannotated CUDA conversion chain was fused into two __byte_perm instructions per four elements; covering scalar and five vector widths of 2, 4, 8, 16, 32; code with explicit conversion annotations retains its original lowering path; the entire conversion completes in registers with no new global or shared memory allocations.

Verification spans four layers: source generation tests cover both E4M3 spellings and all widths; runtime cases compare each packed four-nibble word against an independent encoding table word by word; the extracted GEMM produces bit-identical output to baseline under all configurations (plus an independently sampled CPU reference); current head CI for CUDA, ROCm, Metal, and CuTeDSL all pass.

H100 performance (same card, same inputs, median of 100 calls per figure, four rows excerpted):

M N K Baseline (μs) This PR (μs)
1 2,304 5,120 547.94 108.65
512 2,304 5,120 717.30 224.21
1 5,120 2,304 245.17 45.85
2,048 5,120 2,304 1,760.22 591.92

Speedups across twelve configurations range from 2.97x to 5.38x; register usage rises from 128 to 156 with no spills. Boundaries noted by the author: Blackwell execution and full-model serving remain unverified.

Assessment: A “micro-conversion” with only 161 added lines yields up to 5.4x end-to-end gains, demonstrating that in scenarios like expert GEMM where weights are repeatedly read tile by tile, scrutinizing the cost of the conversion chain is no overreaction; it also once again shows that TileLang’s mainline optimization targets are moving from “large structures” into “the ledger of every layer of instructions.”

I. Core Project Progress

1.1 Main Repo Review Queue: Parallel Loop Fix Newly Opened, TileIR Backend Adds 8 Commits (09-22)

Date: 2026-09-22 to 2026-09-23　Source: #3269 / #3247 and two other PRs (full list in appendix)

  • #3269 (newly opened 09-23 01:48): Lowering fix for parallel loops when let inlining is disabled — adjusts the order of loop variable substitution in PartitionLoop, simplifies buffer indices before substitution, and adds a regression test for parallel loops, plus coverage for conditional parallel loop execution under CUDA/HIP. The same author’s second fix in this window (the previous one being the NVRTC line).
  • #3247 (8 commits added at 13:56): The CUDA Tile IR execution backend (tileir target, lowering to NVIDIA CUDA Tile IR, emitting cubin via the cuTile runtime; includes JIT, caching, autotuning, and a DeepSeek V4 sparse attention tuning kernel) resumed progress after a pause of several days, adding 8 commits in one go this window; still under review.
  • #3267 (updated 09-23 01:05): tl.LowerMagicDiv magic division (host-side precomputation of dynamic-shape divisors) continues in review, covering CUDA/ROCm/CPU C and host code generation.
  • #3265 (updated 13:54): Sinking of launch-invariant integer arithmetic to the host side, covering rejection logic for both the Cython and NVRTC launch paths.
  • #3241 to #3244 (one activity each from 18:16 to 18:20): Four fix PRs remain open with no merge action — CuTeDSL FP4 conversion and store lowering fixes, and the RNG initialization trio (default sequence, void binding rejection, missing-initialization diagnostics).

Queue observation: Only 1 merge in the main repo this window (#3204, see Today’s Highlights); the review side has entered a “add commits, no stamp” state — both the TileIR and magic division lines are stockpiling.

1.2 TileOPs Governance Wrap-up: Last Bypass for Manifest Entries and Evaluators Removed (09-22)

Date: 2026-09-22　Source: TileOPs #2167

Merged at 10:24 (opened 09-21 22:34, completed in about half a day). Following #2158’s manifest formula consolidation, this PR dismantles the mechanism by which “functions silently defer to entries that define an evaluation method” from the installation point: it removes two GQA overrides that blocked the unified path, switching to the same approach of “layering call-time payloads on top of attributes”; it also adds explicit errors for two classes of misuse — payload is None (a caller timing issue) and payload is not a mapping (an author wiring error). Background data comes from the retrospective in the companion PR #2175: at a certain commit point on 09-19, 19 of 175 implemented entries failed formula synthesis; #2158 and this PR fixed them before and after, but at the time no layer would report “who fails next.”

1.3 TileOPs Performance Sprint One: Engram Decode Split into Projection and Reduction Kernels (09-22)

Date: 2026-09-22　Source: TileOPs #2173

Newly opened at 16:50 (1 file +265/-108). The old implementation used one thread block per batch row, with two projections performed as chained scalar loads in a serial loop, and weights not shared across any blocks — on H200 it achieved only 6 to 34 GB/s of the 4.8 TB/s device bandwidth, and was slower than the torch.compile baseline on all manifest workloads. The new structure has two stages: projection is changed to tiling along the d dimension, reading weights once via matrix multiply to serve the entire batch (B no greater than 16 fits in a single MMA tile) while also completing cache shifting; the remaining steps (three RMSNorms, gating, dilated convolution, SiLU) all reduce along d, so they are emitted as a second stage with one block per batch row. One finding is also written into the description: when two matrix multiplies are in the same pipeline body, certain tile shapes silently read the wrong pipeline stage — after sweeping 3 shapes times 30 tile/stage combinations, it was changed to two blocks along the grid axis, and the single-block single-chain version is exact across all 30 combinations.

Measured (H200 device busy time): batch 1 dropped from 28.1 microseconds to 6.0 microseconds (4.7x, reversing from 0.40x to 1.90x versus torch.compile); batch 4 from 67.9 to 8.3 (8.2x, 2.57x); batch 8 from 28.1 to 5.6 (5.0x, 3.16x).

1.4 TileOPs Performance Sprint Two: GEMM Ping-Pong Main Loop Hides Dense Epilogue, 176 Tile Enlisted (09-22)

Date: 2026-09-22　Source: TileOPs #2172

Newly opened at 16:21 (5 files +465/-42). Hides the dense GEMM epilogue under the opposite consumer’s main loop: one producer plus two consumer warpgroups work on alternating persistent loop tiles, with the main loop handing off via ordered mbarriers, so that one consumer’s epilogue runs under the other’s main loop. The accounting works out as follows — in the dual-consumer structure the tensor cores idle during the epilogue, a fixed cost of about 3.1 thousand cycles per tile (5.2 thousand at block width 176), accounting for 9% to 18% of the 32-round main loop, which is exactly the entire gap versus cuBLASLt’s 176x128 kernel on DeepSeek-V3 prefill rows. Supporting changes: the epilogue is changed to rotate between two scratch tiles (previously the last unhidden epilogue serialized eleven write-backs, each launch costing an extra 2.9 thousand cycles), M/N tails go through TMA boundary clipping, and a 176 bucket width is enlisted (2112 = 12 times 176, last wave 91% full, better than 192’s 67%). 176 requires tilelang no lower than 0.1.14 (depends on select_wgmma_inst_n); a version floor is added to pyproject.toml and enforced in the install script. Testing: 86 items pass on H200, six shapes are bitwise identical to torch.matmul, and 9 new tests are added.

1.5 TileOPs Performance Sprint Three: GLA Inference Operator Enlisted, MoE Excess Routing Grouping (09-22)

Date: 2026-09-22　Source: #2174 / #2169 / #1931

  • #2174 (newly opened 17:07, 15 files +1384/-2, draft label not listed): GLA inference operator (GLAInferenceFwdOp, BTHD layout Q/K/V/G, optional FP32 initial state, returns output and FP32 final state). Replaces serial intra-chunk scoring with 16-token tensor core tiles; the long-sequence path absorbs the partition summary/scan/replay approach from #1931, enabled only when sequence length is at least 16384. Measured on H200 (batch 2, length 16384, 4 heads, Dk=Dv=64): old chunked path 472.1 microseconds, partitioned path 348.5 microseconds, reference implementation 443.5 microseconds; the manifest benchmark independently measured TileOps at 392.0 versus reference 531.5 microseconds. Short sequences keep the original path.
  • #2169 (newly opened 12:58): Grouping optimization for the MoE index path when a single expert receives more than 16 routes — chooses between indexing and contiguous execution based on routing density rather than token count; measured on H200 at the 64-token tier: DeepSeek-V3 rises from 0.80 to 0.990 (relative to vLLM, values greater than 1 meaning faster), Kimi-K2 from 0.83 to 0.993, GLM-4.5 to 0.995; the 32-token tier rises to near 1.0. Duplicate PR #2171 on the same topic was closed three minutes after opening.
  • Three closed: W4A16 GEMV acceleration (#2159) and W4A16 grid K-splitting (#2170), two performance explorations, were closed; the GLA prefill pipeline (#1931), opened 08-17, was closed, its partitioned scan approach having been absorbed by #2174.

Three performance PRs in one day (Engram, GEMM, GLA) plus one MoE optimization all in play at once makes this TileOPs’ densest performance submission day in recent memory.

1.6 TileOPs: Roofline Synthesis Failures Made Reportable, Three Queue Updates (09-22)

Date: 2026-09-22　Source: TileOPs #2175

Newly opened at 19:47 (8 files +473/-160). Directly addresses the problem of “formula synthesis fails but cannot be reported”: previously an entry whose evaluation could not be synthesized only showed a placeholder hint, and the message actually pointing out the illegal name or construct was thrown by the code generation layer with no one to receive it; the code generation layer itself did not render a verdict for every entry (non-mapping signatures threw bare exceptions, and for module-level attribute services, anything thrown counted); and the synthesis process imported the output dtype resolver to bind a single name, dragging in the entire tensor library — checking formula names and forms should not require torch. This PR makes the code generation layer’s gate a full verdict (every malformed entry is an explicit error naming the operator), makes the verdict read only the entry itself (all 175 implemented entries are synthesizable in a torch-free environment), and adds a per-entry synthesis check that reports the reason for failure as a schema-level error. It also corrects six statements in the design document that did not match the code.

Queue updates: #2168 (W4A16 prepacked weight order, updated 23:55) remains open; #2163 (DeltaNet inference operator, updated 23:36) and #2160 (variable-length GQA migration, updated 23:19) both made progress.

1.7 TileFoundry: Two Merges for Memory Metadata and Traffic Normalization (09-22)

Date: 2026-09-22　Source: TileFoundry #175 / #176 / #168

  • #175 (merged 12:09): Analysis supports loop start points with unit-dependent dependencies — when upper bounds and step sizes carry unit semantics, it no longer assumes a start of zero, aligning the analysis semantics with the loop semantics of hardware execution.
  • #176 (merged 15:22, two commits): Memory metadata and traffic normalization — rewrites the analysis memory and metadata modules, touching traffic accounting, roofline, and the analysis specification document (the analysis specification single file changed 263 lines), and synchronizes tutorials and checkers. Both were opened on 09-21 and merged the same day (completed within one day).
  • Related PRs: #171 and #173 closed; #168 (repeated reads of invariant operands should count toward total traffic) remains under discussion.

1.8 Nightly Snapshot: 1046 Benchmarks Zero Failures, 1141 Correctness Items Resume Publication (09-23)

Date: 2026-09-23　Source: Snapshot commit 81946098 / Snapshot environment metadata

Generated at 02:38 for b07a259f (#2167 merge point): 1046 benchmarks, 0 failures, 3 skipped (still the three GQA paging items), case count on par with the previous snapshot; the correctness results file is republished this time — 1141 items, 0 failures, 2 skipped, resolving the suspicion about the missing file in the previous two snapshots (the 09-21 snapshot shipped only the benchmark file). Environment is consistent with the previous period: H200, CUDA 13.2, driver 595.71.05, TileLang 0.1.11 plus codename version, torch 2.13.0, image codename afcebed1 second edition.

II. Multi-Backend Adaptation (Ascend / Hygon / MetaX / Moore Threads, etc.)

2.1 Ascend: Daily test reproduces workflow-level failure, three new defect tickets point to A5 hardware path and auto-sync (09-22 to 09-23)

Date: 2026-09-22 to 2026-09-23　Source: Daily test #1831／#1830／#1824／#1825

  • Daily test reproduces failure (#1831, auto-filed 09-23 06:29): the batch job ran for about an hour and a half before ending in failure (workflow-level failure, not case-level); by contrast, the 09-22 06:35 snapshot was 2448/2448 all green. The past three days have alternated red and green (09-21 workflow failure, 09-22 all green, 09-23 failure), and the stability issue warrants continued observation. No pushes to the code branch in this window.
  • #1830 (filed 09-23 00:47): architecture label defect on the A5 device path — on a real Ascend 950 (dav-3510), the device path compiles with the fixed label dav-2201 (belonging to the 910B generation), and the kernel reports device exception 507015 immediately on launch; after changing the label the kernel launches, but silently computes wrong values (the scaling factor in the official quantization example is wrong). The author identifies the root cause as a hardcoded architecture label in the build code, and notes that the README’s verification matrix happens to bypass that label in both directions (real hardware A2/A3 are already 910B generation, and A5 only runs in simulation), which is why it went undetected.
  • #1824 / #1825 (filed 09-22 09:58, same reporter): two edge cases in auto-sync — sync state inside conditional branches is incorrectly merged, so subsequent reads may lack a barrier when the branch is not executed (includes a minimal reproduction); auto cross-core sync should reject at compile time both configurations where “a combined switch being off causes the switch to silently fail” and where “automatic and hand-written sync are mixed.” The latter points out that examples in the repo itself contain such configurations.

2.2 MLIR Ascend: Large Mamba SSD chunk scan operator merged, tuning and integration flow also refined (09-22)

Date: 2026-09-22　Source: tilelang-mlir-ascend #191

Merged at 18:57 (opened 15:18, completed in about 3.5 hours, 42 files +4204/-1568). The Chinese title serves as the change description, covering three parts: first, NPU expert kernel optimization of the Mamba-2 state space dual (SSD) chunk scan and its integration into the wrapper layer — improved prior-state loading, L0C double-buffered computation, vector branch data reuse, with synchronized updates to default configuration, design docs, and tuning logs; second, refinement of the operator flow — correcting load distribution and benchmark case selection for optimization tasks, generating load lists from benchmarks, recording performance results by actually tested kernel files, and validating final files, test coverage, and report data in the gate; third, adding automatic generation and validation of TileOPs reports, automatically setting mode variables during integration, and distilling conclusions from SSD reruns and second-round tuning into the mode library, cases, and to-do records. This change echoes the Mamba line in the Ascend adaptation repo within the same window, as well as the chunk scan work in the community TPU repo (see 2.5).

2.3 Hygon: FP32 MMAC K commit extension redone; example support PR adds 32 files (09-22)

Date: 2026-09-22　Source: Branch commit e4dc1053／Example support PR #11

  • Feature branch redone (pushed 15:27): the fix on the feat/hcu-ds-read-fp32-mmac-k branch was extended and redone — the original three-file version (shared FP32 MMAC K and fragment packing) was expanded to a five-file version (+54/-86): adding removal of the FP16/BF16 datatype restriction in GEMM’s LDS strategy derivation (broadening the strategy’s applicability and clearing a prerequisite for the FP8 path), and cleaning up the FP8 export workaround in the tvm_ffi adapter (53 lines deleted, 4 added; originally used to bypass the limitation that torch FP8 cannot be exported via DLPack); the commit dates to the evening of 09-21, with the push landing in this window. The branch still has no corresponding PR.
  • Example support PR #11 extension (additional commit 14:44, 32 files +1086/-121): opening up Hygon support for TileLang upstream examples — adding HCU-specific flash attention examples (forward 258 lines, backward 603 lines) and their tests; batch-adapting upstream examples including attention (multi-head forward/backward, GQA decoding and variable length, block sparse), MoE chunked state, GEMM (auto-tuning, persistent, inline primitives), GEMV, and grouped matrix multiplication; CI workflows and regression scripts updated in sync, and introducing precompiled flash-attn wheels from a domestic mirror.

2.4 MetaX and Moore Threads: No pushes in window (09-23 check)

Date: 2026-09-23 (check)　Source: tilelang-metax／tilelang-musa

MetaX’s most recent push remains 09-21 (upstream sync), and Moore Threads’ most recent push is 09-17; neither repo saw new activity in this window. One further sign of ecosystem warmth on the MetaX side: a community training camp continues to submit materials using C500 plus TileLang as its teaching vehicle (see 3.2).

2.5 Community backend: TileLang-TPU advances Sophgo BM1690 multi-core validation and performance matrix (09-22)

Date: 2026-09-22　Source: Community repo TileLang-TPU

A community TileLang extension repo targeting Sophgo accelerators pushed three commits in this window: multi-core chunk scan S3 and P6 validation (14:27), the P10 performance matrix (16:05), and a P10 host-side source validation fix (16:13). The repo positions itself as “bringing the TileLang programming model to Sophgo TPU targets” — retaining TileLang’s Python frontend, adding TPU lowering, code generation, and JIT runtime integration, providing a target="tpu" target, two execution modes (PCIe and simulation), and TPU-specific primitives (copy, matrix multiply, reduction, reciprocal square root, rotary position embedding, etc.), with BM1690 as the main line, having entered hardware validation and level-by-level tuning since 09-20 (single-core, multi-core, performance roadmap P8 to P10). The repo is under active development and declares submissions welcome. This is the first publicly visible TPU backend path in the TileLang community; in contrast with the Mamba chunk scan merge in MLIR Ascend within the same window, the same algorithm family appeared on two non-NVIDIA targets on the same day.

III. Ecosystem and Adopters

3.1 Adopters: TileKernels and FlashQLA no pushes in window (09-23 check)

Date: 2026-09-23 (check)　Source: TileKernels／FlashQLA

Neither adopter pushed in the window: TileKernels’ most recent push stopped at 04-23; FlashQLA’s last push was 09-18. Notably, the FP4-to-FP8 fusion merged into the main repo in this window targets DeepSeek V4.1’s expert GEMM — the adopter did not touch code, but the conversion pattern in its inference code directly drove the upstream optimization.

3.2 Community project: MetaX C500 multi-paradigm operator development bootcamp materials continue to be submitted (09-22)

Date: 2026-09-22　Source: Community training camp materials repo

Two commits in this window: completing the second lecture’s “vector addition” comparative exercise with TileLang and Jiuchi dual implementations (10:29), and supplementing the remote instance workflow with operational agent skill configuration (10:32). This materials repo uses MetaX C500 compute as its base (the image contains TileLang 0.1.9 and a specific toolchain version), with the exercise sequence being: device and compute environment, TileLang vs. Jiuchi addition comparison (tiling and tail blocks), reduction and numerical stability for Softmax and GEMM, AI agent-assisted operator development and validation, then moving into the Llama operator stage (integration, correctness, performance, end-to-end). The repo’s history shows traces of upstream branch merges with the community compute program, representing sustained investment in the community teaching direction.

IV. Community, Tutorials, and Events

4.1 Documentation site: One versioned deployment of the TileOPs documentation site (09-22)

Date: 2026-09-22　Source: TileOPs documentation site

One automated deployment at 08:40 (static site generator 1.6.1 versioned commit), with no substantive change to site content; the main repo’s documentation site saw no deployment in this window.

4.2 Media and academia: Zero Google News hits, no new arXiv papers (09-23 check)

Date: 2026-09-23 (check)　Source: Google News RSS (multiple Chinese and English queries, via proxy)／Hacker News／arXiv

Zero hits across multiple Chinese and English Google News queries in the window; Hacker News related queries returned only unrelated entries (coincidental matches on terms like PCB routing and desktop gimbals); the latest arXiv topic search result remains the 07-24 performance model paper, with no new preprints in the window. The second consecutive quiet window on the media side.

4.3 Release cadence: No new releases, main repo v0.1.14 now 21 days old (09-23)

Date: 2026-09-23　Source: tilelang v0.1.14

No new releases from any repo in the window. The main repo’s latest release remains v0.1.14 from 09-02 (now 21 days old); adaptation line versions are unchanged: Ascend v0.1.2.000 (09-09), MLIR Ascend v0.1.2.020 (09-09), Moore Threads v0.1.14+musa.1 (09-11), MetaX v0.1.14 (09-17), Sunrise 0.1.14+sunrise.1.1.0 (09-21). Also note: as of #2172, TileOPs imposes a hard minimum requirement of tilelang version 0.1.14, and the relationship between release cadence and downstream adoption windows is worth watching.

V. Trend Observations

5.1 Conversion operators become first-class citizens

A 161-line change concerned solely with “how FP4 becomes FP8” yields a 2.97x to 5.38x end-to-end speedup, provided it appears on a repeatedly read weight path. In parallel, TileOPs’ three performance tickets (Engram splitting, GEMM transfer hiding, GLA chunking) are all optimizing “how many times the same block of data is read and at which cache level it flows.” As operator-level structure gradually stabilizes, gains continue migrating toward data movement and format conversion — which also explains why the main repo would merge a precise encoding conversion as a legitimate entry rather than a local tweak.

5.2 TileOPs shifts from governance season to performance season

Last week’s keyword was “fixing what’s wrong” (formulas, physics, provenance); in this window, three performance tickets plus one routing optimization are present simultaneously within a single day, and newly filed tickets generally come with their own comparison baselines (torch.compile, cuBLASLt, reference implementations, vLLM) and bitwise-consistency declarations. The ledger left by governance is turning into a credit asset for performance work: each performance ticket can be independently verified against the checklist and benchmarks.

5.3 Ascend’s red-green alternation and A5’s real-hardware test

The red-green alternation over three days of daily tests shows the batch environment’s stability is still not closed out; and the problem exposed by #1830 is more representative — the verification matrix covers the 910B generation with real hardware and the 950 generation with simulation, and both sides happen to bypass the device path’s architecture label, causing the defect to surface on a real 950 in two forms: “crash on launch, silent miscalculation after changing the label.” The depth of cross-generation hardware adaptation is moving from “can compile” into the stage of “daring to calibrate on real hardware.”

5.4 Gaps and risk points

Four points: first, the main repo merged only one change in this window, and both major lines — TileIR and magic division — are in a “seasoned but not stamped” state, so whether review bandwidth has become a bottleneck is worth observing; second, the release freeze has now lasted 21 days, while downstream (TileOPs) has begun declaring a hard dependency on 0.1.14 and above, so the cadence between the version window and ecosystem adoption needs coordination; third, the Ascend A5 output correctness issue (silent errors after changing the label) still has no fix ticket, and if confirmed it would affect the credibility narrative for the 950 generation; fourth, the Hygon feature branch still has no PR, and the reverted large Ascend merge has no visible rework schedule, so the “landing in progress” state continues for both domestic lines.

Appendix: Sources and Verification Notes

Source Verification Table

Source Verification Result
tile-ai organization (28 repos) 7 repos had pushes within the window: tilelang, TileOPs, TileOPs-nightly, TileFoundry, tilelang-mlir-ascend, tilelang-hygon, TileOPs.github.io
Main repo tilelang default branch 1 merge (#3204); 1 new open (#3269); #3247, #3267, #3265, #3241 through #3244 each had updates within the window; 0 new and 0 closed issues within the window
TileOPs 1 merge (#2167); new open #2169, #2172, #2173, #2174, #2175 (plus #2171, a duplicate of the same topic, closed on the spot); closed #2159, #2170, #1931; #2168, #2163, #2160 updated
TileOPs-nightly 1 snapshot (81946098, corresponding to b07a259f, i.e., the #2167 merge point): 1046 benchmarks with zero failures; 1141 correctness items restored and released with the snapshot
TileFoundry 2 merges (#175, #176); #171, #173 closed; #168 remains under discussion
tilelang-mlir-ascend 1 merge (#191, Mamba SSD chunk scan optimization, 42 files)
tilelang-hygon 2 branches had pushes: feature branch commit extension rework, example support PR #11 appended with a 32-file commit
tilelang-ascend No pushes on code branches; daily test workflow-level failure (#1831); 3 new defect tickets (#1830, #1824, #1825)
Other tile-ai repos (TileRT, tilescale, DeepStack, tilelang-puzzles, metax, musa, etc.) No pushes within the window
Adopters (TileKernels, FlashQLA) No pushes within the window
Third-party discoveries Community TPU extension repo (BM1690 multi-core verification, 3 commits); community training camp materials repo (2 commits)
Google News / Hacker News / arXiv Zero hits across multiple Chinese and English queries; no related HN entries; no new arXiv preprints

Complete Source List