Research window: 2026-10-30 07:00 ~ 2026-11-02 07:00 (Beijing time, 72 hours, covering the weekend; the previous issue’s cutoff was 10-30 07:00).

Sources: GitHub tile-ai organization repo-by-repo verification (tilelang / TileOPs / TileFoundry / tilelang-ascend / tilelang-mlir-ascend / tilelang-hygon / tilelang-metax / tilelang-musa / TileRT / tilescale / DeepStack / TileOPs-nightly / documentation site) + ground-truth search of merged and in-review items (35 merged, 82 in-review updates) + full verification of new issues (11) + commit-by-commit verification on main branches (tilelang 7, TileOPs 15, TileFoundry 3, tilelang-ascend 5, tilelang-hygon 2, tilelang-mlir-ascend 1, documentation site 4) + release page and tag verification (6 repos) + third-party ecosystem repo verification (FlashQLA, TileKernels, three RISC-V research-chain repos, PTO-ISA/tilelangGym) + Google News Chinese and English queries (via proxy) + Hacker News + arXiv.

Issue Index

  • Today’s Focus: The mainline is the rollback of TIRX migration to ThreadSync’s precise thread counting (#3733), with a new tracking issue acknowledging that correctness improvements are being withdrawn alongside it; TileOPs merged 13 performance PRs in a single day; Ascend host-side fixed overhead cut from ~450 µs to ~106 µs; 35 merges, 82 in-review updates, and 11 new issues over 72 hours
  • I. Core Project Progress
    • 1.1 Mainline: Rollback of ThreadSync’s precise thread counting to make way for the TIRX migration (#3733) (11-01)
    • 1.2 Mainline: CUDA cross-warp all-reduce consolidated into a single shared-memory exchange, 256 threads drop from 6 barriers to 2 (#3715) (10-30)
    • 1.3 Mainline: First milestone for T.Parallel vectorization on the PTO backend, elementwise operators use VMI instructions (#3512) (10-30)
    • 1.4 Mainline: Ascend DeepGEMM’s scale buffer switches to write-counted multi-buffering, data loads can be hoisted ahead of conditional loads (#3629) (10-30)
    • 1.5 Mainline: Two fixes merged, CPU scalar GEMM clears only the target region, negative-index legalization skips unreachable branches (#3709 / #3712) (10-30)
    • 1.6 Mainline: Language layer removes two unused Ref placeholders in proxy (#3722) (10-31)
    • 1.7 New defects and in-review: TMEM silently drops results, ROCm symbol not found, TF32 round-to-nearest-even (#3721 / #3711 / #3714) (10-30 ~ 10-31)
  • II. Multi-Backend Adaptation
    • 2.1 Ascend: Cython wrapper lazily constructs TVM Analyzer, 910B3 single call drops from ~450 µs to ~106 µs (#1948) (10-30)
    • 2.2 Ascend: RFC proposes replacing the sync implementation with the mainline core plus a standalone Z3 proof service (#1971) (10-30)
    • 2.3 Ascend in review: Migrate TileLang-Ascend wholesale to the mainline multi-backend architecture (#1975) (10-31)
    • 2.4 Ascend in review: GLM-5.3 kpool fp8_mqa_logits example, dual kernel with AIV/Cube division of labor (#1966) (10-31)
    • 2.5 Ascend: Four documentation and API fact-check merges, clamp now actually takes effect on PTO (#1899 / #1893 / #1620 / #1600) (10-30)
    • 2.6 Ascend: All 2970 daily test cases pass, one workflow failure on 11-01 (#1977 / #1976) (10-31 ~ 11-02)
    • 2.7 Hygon: MLS boundary and continuous WASP sync fixes merged, gfx948 compatibility in review (#31 / #32) (10-30)
    • 2.8 mlir-ascend: CI removes internal cache service references, Codex workflow in review (#206 / #208) (10-31)
    • 2.9 Moore Threads and MetaX: no pushes during the window (11-02)
  • III. Ecosystem and Adopters
    • 3.1 TileOPs: 15 merges in 72 hours, 13 landed on 11-01, nearly every one with a measured table and manifest regression gate (11-01)
    • 3.2 TileOPs: GQA dense forward uses a single measured rule to select decode or prefill programs, selection regret drops from 1.818 to 1.017 (#2808) (11-01)
    • 3.3 TileOPs: Paged MHA decode extended to every head dim that fits in shared memory, GQA paged forward drops the old decode kernel (#2807 / #2797) (11-01)
    • 3.4 TileOPs: coop2 producer reduced to a single warp, new 192-wide transpose block, W4A8 partial wave changed to one CTA per tile (#2806 / #2805) (11-01)
    • 3.5 TileOPs: Compile cache keyed by build target, operator layer uniformly checks output-input overlap (#2802 / #2801) (11-01)
    • 3.6 TileOPs defect in progress: Four Norm operators lose precision on rows far from zero, overflow to NaN at ~1e36 (#2812) (11-01)
    • 3.7 TileFoundry: Lowering consolidates issuing mesh and window splitting into a single decision point, 83 scheduling fixtures byte-identical (#280 / #282) (10-31 ~ 11-01)
    • 3.8 TileFoundry: Site publishes v0.3 scheduling article “Scheduling, Designed for Agents” (#4 / #281) (10-31 ~ 11-01)
    • 3.9 Adopter: FlashQLA merges SM120 Dual-CP forward and backward, compares against Inter-CP on 2× RTX 5090 for 32K to 128K sequences (#51) (10-30)
    • 3.10 Adopter: TileKernels has had no pushes since 10-14 (11-02)
  • IV. Community, Tutorials, and Events
    • 4.1 RISC-V research chain takes shape: Three repos convert Numba CUDA Python to TileLang, then lower restricted PrimFuncs to single-hart RVV C (10-31)
    • 4.2 PTO-ISA/tilelangGym spun out from PTO-ISA/tilelang into its own repo, main regression gate is the Ascend SimtVF path (10-30)
    • 4.3 News side: Google News Chinese and English queries, Hacker News, and arXiv all show no substantive hits within the window (11-02)
  • V. Trend Observations
  • Appendix: Sources and Verification Notes

Today’s Focus

The heaviest action in this window is subtraction. The mainline rolls back in full the precise thread counting merged three weeks ago (#3291) (#3733), with a plainly stated rationale: that change moved expensive counting queries ahead of full-block barrier checks, so even when all threads will reach the barrier the proof still has to run; the current TVM solving budget gets exhausted and returns partial counts, causing otherwise legal remap and sequence helper kernels to fail compilation outright with “Cannot prove a thread rectangle.” The rollback proceeds on both ThreadSync implementations, deletes the tests introduced by #3291, and adds a reduction case where the loop is empty for most threads yet all 256 threads still reach the barrier; correctness improvements such as the quotient guard, precise participating-thread bounds, and non-rectangular thread sets are also withdrawn, with newly opened #3732 kept as a tracking issue for re-optimization after the migration. This is an explicitly labeled migration concession: TileLang is preparing the TIRX migration to shed its current TVM fork dependency, and the accompanying TVM fork optimization proposal has been closed.

The second thread is Ascend shoring up its foundations. #1948 fixes a host-side fixed cost independent of operator size: the Cython wrapper unconditionally constructs a TVM Analyzer on every call, measured at about 0.28 ms per call on 910B3, yet it is only needed when shapes are symbolic expressions; after switching to lazy construction, vec add single-block drops from 442–467 µs to 105.1 µs, 32-block drops from 441–493 µs to 108.0 µs, and kpool compression drops from 447–450 µs to 111.3 µs, while the bare ctypes call serving as a lower bound stays unchanged at about 12 µs. Meanwhile, the RFC in #1971 lays out a replacement path for the sync implementation: port the mainline sync core plus a standalone Z3 proof service, wire it into the existing compilation pipeline via a legacy TIR adaptation layer, preserve TVM, scheduling, memory planning, AscendC/PTO codegen, and the runtime ABI, then switch the default implementation and delete the old algorithm once acceptance passes—two landing points of the same effort as #1975’s migration of the entire Ascend repo to the mainline multi-backend architecture.

The third thread is in the operator libraries. TileOPs merged 13 PRs on 11-01 alone, almost all performance patches, each with an H200 measured table and a manifest regression gate. Among them, #2808 reduces GQA dense forward program selection to a single rule, cutting selection regret relative to the fastest candidate program from 1.818 to 1.017 (2 to 128 query positions, 586 calls), and fixes a real mainline bug: the score scale vanishes in FP32 after multiplying by log2(e), turning outputs into NaN or wrong values.

I. Core Project Progress

1.1 Mainline: Precise thread counting rollback in ThreadSync to make way for the TIRX migration (#3733)

Merged on 11-01 14:50. The reverted #3291 moved precise thread counting ahead of the full-block barrier check and added rectangle certification, at the cost of running CountSatisfyingValues even when all threads reach the barrier; once the TVM-side solving budget is exhausted it returns a partial count, and the remap and sequence helper kernels then fail with “[ThreadSync] Cannot prove a thread rectangle”. The regression reproduces on mainline cc903dcb9 with the unchanged TVM pin 4211874e9e, and the new test case reduces it to “loop empty for most threads, yet all 256 threads still reach the barrier”. The rollback covers both the shared and Ascend implementations, restoring the full-block fast path and the old partial-count behavior; the description explicitly states this is a temporary mitigation during the TIRX migration, the optimization proposal tile-ai/tvm#89 on the TVM fork side has been closed, and follow-up optimization moves to #3732.

Source: https://github.com/tile-ai/tilelang/pull/3733

1.2 Mainline: CUDA cross-warp full reduction merged into a single shared memory exchange, cutting 256 threads from 6 barriers to 2 (#3715)

Merged on 10-30 20:26. The old implementation in the CUDA reduction header reduce.h recursed from threads/2 down to scale, performing a full shared memory write-read exchange plus two barriers at every step with offset not less than 32: a 256-thread block’s three steps (128, 64, 32) totaled 3 shared memory round trips and 6 barriers, and a 512-thread block had 4 and 8. The change compresses all cross-warp steps into a single exchange (one st.shared per element, 2 barriers total): first do the scale < 32 segment within the warp, then have up to cross_radix lanes in each intra-warp group cooperate to fold, with bounded register pressure. Both the scalar and batched paths were changed.

Source: https://github.com/tile-ai/tilelang/pull/3715

1.3 Mainline: First milestone of T.Parallel vectorization on the PTO backend lands, elementwise operators run VMI instructions (#3512)

Merged on 10-30 01:29. The goal is to let users write scalar-parallel elementwise T.Parallel inside T.SimdVF(lanes=L), have the compiler vectorize it into PTO VMI instructions, and execute on Ascend 950 via PTOAS. The division of labor is clearly specified: the TileLang side handles logical lane layout inference, the vectorization pass pipeline, VMI instruction generation, and Fragment logical mapping; the PTOAS side handles physical register partitioning, mask materialization, Fragment buffer and vector register allocation, and mem_bar insertion. The roadmap has five milestones; this PR is the M1 core framework (elementwise computation, covering both cases of whether extent is divisible by lanes), with M2 control flow, M3 reduce, M4 UB capacity planning and register allocation, and M5 non-contiguous access and wider PACK data types following in order.

Source: https://github.com/tile-ai/tilelang/pull/3512

1.4 Mainline: Ascend DeepGEMM scale buffer switches to write-count multi-buffering, allowing data loads to be hoisted before conditional loads (#3629)

Merged on 10-30 05:48. DeepGEMM reuses scale factors across multiple K blocks; this PR adds an explicit write-count multi-buffering mode so the scale buffer version advances on actual writes: within each owner loop iteration it advances only once at the first write task actually executed, subsequent writes share that version, iterations with no write retain the old value, and multiple disjoint owners and shared clocks are supported. This allows data loads to be scheduled before the conditional scale load; it also flattens DeepGEMM’s K loop, fetching data before scale on both L1 and L0, and adds test cases for guard updates, nested updates, retained reads, flag and buffer reuse, and FP4’s K-major and MN-major with tail blocks and ring wraparound. This mode requires an explicit version count and assumes at most one update per owner iteration.

Source: https://github.com/tile-ai/tilelang/pull/3629

1.5 Mainline: Two fixes merged, CPU scalar GEMM clears only the target region, negative index legalization skips unreachable branches (#3709 / #3712)

Both merged on 10-30, landing the items under review in the previous issue. #3709 makes CPU scalar GEMM clear only the target region, where it previously also cleared ranges not belonging to this output; #3712 makes LegalizeNegativeIndex skip unreachable branches, avoiding negative index rewriting of code that will not execute. These two belong to the same batch of defect cleanup as #3708 and #3710 reported in the previous issue, of which #3708’s bit-width change to int64 and #3710’s bypassing of the two in-process caches when caching is disabled are still under review.

Source: https://github.com/tile-ai/tilelang/pull/3709, https://github.com/tile-ai/tilelang/pull/3712

1.6 Mainline: Language layer removes two unused Ref placeholders in proxy (#3722)

Merged on 10-31 17:31. tilelang/language/proxy.py contained two Refs at once: a tirx.Var stub for type checking and an empty runtime class, neither of which has any consumer in the tree; the public T.Ref actually comes from eager.builder, whose implementation is the real body of the macro reference parameter. This PR deletes both placeholders, the _T type variable, and the now-useless Generic and TypeVar imports, preserving T.Ref and macro reference behavior while removing only the unused direct import path tilelang.language.proxy.Ref. The 179 frontend construction tests pass with 6 skipped, and a runtime identity check confirms T.Ref is still eager.builder.Ref.

Source: https://github.com/tile-ai/tilelang/pull/3722

1.7 Newly filed defects and under review: TMEM silently drops results, ROCm symbol not found, TF32 round-to-nearest-even (#3721 / #3711 / #3714)

#3721 is the most alarming item this window: doing T.gemm on TMEM on sm_100a, when threads/32 does not divide N, compilation succeeds but the PTX contains not a single tcgen05.mma, and T.copy(Ct, Cl) reads TMEM that nobody wrote, so the product is silently dropped; in the reproduction threads=256 yields one instruction and threads=384 yields zero, and the author suspects src/cuda/op/gemm.cc returns a {1, num_warps} partition for TCGEN05 without a coverage check. #3711 reports kernels failing with “named symbol not found” under the ROCm 7.14 and 10.0 PyTorch wheels. #3714 is under review, adding round-to-nearest-even to the fp32 to tf32 conversion (cvt.rn.tf32.f32 and the saturating form), with the non-saturating form requiring SM90 or above and the saturating form requiring SM100 or above, closing the corresponding feature request #3713.

Source: https://github.com/tile-ai/tilelang/issues/3721, https://github.com/tile-ai/tilelang/issues/3711, https://github.com/tile-ai/tilelang/pull/3714

II. Multi-Backend Adaptation (Ascend / Hygon / Moore Threads / MetaX)

2.1 Ascend: Cython wrapper lazily constructs TVM Analyzer, 910B3 single call drops from ~450 µs to ~106 µs (#1948)

Merged on 10-30 07:44. CythonKernelWrapper.forward() previously constructed a TVM Analyzer() unconditionally on every call, a fixed host overhead of ~0.28 ms on 910B3, even though the object is only needed when the result or workspace shape is a symbolic expression; static-shape kernels never use it yet paid the same cost. The fix defers construction into the tir.PrimExpr branch and reuses it on demand. Measured: vec add single-block 442–467 µs down to 105.1 µs, 32-block 441–493 µs down to 108.0 µs, kpool compression 447–450 µs down to 111.3 µs, raw ctypes call ~12.5 µs down to ~12 µs. Two regression tests added, verifying that the static path does not construct and the symbolic path constructs on demand.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1948

2.2 Ascend: RFC proposes replacing the sync implementation with the mainline core plus a standalone Z3 proof service (#1971)

This RFC does not presuppose a speedup conclusion; it only fixes the comparison baseline: the Ascend repo sits on TileLang 43b0b69 and TVM c2921fd with the old tvm.tir as its IR foundation; mainline sits on TileLang 1c0f402 and TVM 4211874e9e with tvm.tirx and tvm.s_tir as its IR foundation, and its object and registration systems have also moved to the new FFI and reflection facilities. Migration therefore cannot be reduced to copying a single InsertSync file. The proposed route is to port the mainline sync core and the standalone Z3 proof service, wire them into the existing compilation pipeline through an old-TIR adaptation layer, and preserve the existing TVM, scheduling, memory planning, AscendC/PTO codegen and runtime ABI; only after acceptance on supported scope, correctness, performance and installation should the default implementation be switched and the old sync algorithm deleted. Companion PR is #1965.

Source: https://github.com/tile-ai/tilelang-ascend/issues/1971

2.3 Ascend under review: migrate TileLang-Ascend wholesale to the mainline multi-backend architecture (#1975)

Proposed 10-31 and continuously updated, the goal is to migrate TileLang-Ascend onto TileLang mainline’s multi-backend architecture per proposal #1911; the description provides two diff comparisons, one against the ascendc_pto branch and one against mainline. This and the RFC in 2.2 are two layers of the same convergence path: one changes the sync algorithm, the other changes the repo’s skeleton.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1975

2.4 Ascend under review: GLM-5.3 kpool fp8_mqa_logits example, dual-kernel with AIV/Cube division of labor (#1966)

An Ascend version modeled on the GLM-5.3 fp8_mqa_logits example under the main repo’s kpool directory. The operator semantics are the pooled history scoring of the GLM-5.3-Flash sparse attention indexer: for each query row, within the valid pool range, read E4M3 keys from 64-pool pages via the page table (uint8-carried bytes plus fp32 scale), dequantize, compute MQA scores for 32 indexer heads, multiply by per-pool scale, and reduce via a ReLU gate and per-head weighting to one FP32 logit per pool, outputting negative infinity for out-of-range or invalid pages. The implementation uses two kernels: a mask kernel generates per-lane 0 or negative-infinity masks per 64-pool tile to replace host pre-fill, and the main kernel assigns one block per row per page, with two AIVs each handling a 32-pool half-page while Cube reads the full page for a single 64×32×128 GEMM. Head count 32, dimension 128, page size 64.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1966

2.5 Ascend: four documentation and API fact-check PRs merged, clamp now actually takes effect on PTO (#1899 / #1893 / #1620 / #1600)

All four merged on 10-30 as part of the ongoing API fact-check batch: #1899 verifies the T.tile.bitwise_xor docs (a re-submission of #1681), #1893 verifies T.tile.bitwise_rshift (a re-submission of #1676), #1620 makes T.tile.clamp actually take effect on PTO and syncs the docs, adding tests and API docs, and #1600 updates the axpy docstring, strengthens tests and adds API docs. Also under review in the same batch are #1968, #1967 and #1974: halving the sigmoid and round counts, symbolic shape parsing caching, and a fix for tile size being incorrectly halved under whole-block row splitting.

Source: https://github.com/tile-ai/tilelang-ascend/pull/1620, https://github.com/tile-ai/tilelang-ascend/pull/1899

2.6 Ascend: daily test 2970 cases all pass, one workflow failure on 11-01 (#1977 / #1976)

The 11-02 06:42 daily test record shows 2970 items, 2970 passed, 0 failed, a 100% pass rate; the 10-31 06:56 run was likewise 2970 items all passing. In between, the 11-01 05:08 run was marked as a workflow test job failure, coinciding with the #1975 migration changes and the #1971 RFC in this window — a fluctuation to watch rather than a stable regression.

Source: https://github.com/tile-ai/tilelang-ascend/issues/1977, https://github.com/tile-ai/tilelang-ascend/issues/1976

2.7 Hygon: MLS boundary and persistent WASP sync fixes merged, gfx948 compatibility under review (#31 / #32)

#31 merged on 10-30 10:56 with three items: improved dynamic MLS boundary inference and MatrixStore stride handling; a fix for sinking clear_accum in MMAC and blockscaled GEMM; and switching the persistent WASP path to M-partitioned consumers with independent A/B fences, while retaining slot and phase rotation and adding synchronization for tail consumers. #32 is under review, treating gfx948 as gfx946-compatible so existing instructions run directly on the new model. The ordinary-copy LDS swizzle (#30) reported in the previous window has landed in the same period.

Source: https://github.com/tile-ai/tilelang-hygon/pull/31, https://github.com/tile-ai/tilelang-hygon/pull/32

2.8 mlir-ascend: CI clears internal cache service references, Codex workflow under review (#206 / #208)

#206 merged on 10-31 07:24, clearing CI content pointing at an internal cache service — a reproducibility cleanup. #208 is under review, adding the first batch of Codex workflows to Operator Harness: completing project initialization via iterative questioning, onboarding existing operator repos, and resuming development, tuning or analysis from persisted context; the three skills share editable Markdown records under .workspace/, task handoff distinguishes “current candidate” from “verified best candidate”, and failed and rolled-back experiments are retained. The author explicitly notes there is no real NPU testing this time, with NPU execution adaptation and npm distribution listed as follow-up work.

Source: https://github.com/tile-ai/tilelang-mlir-ascend/pull/206, https://github.com/tile-ai/tilelang-mlir-ascend/pull/208

2.9 Moore Threads and MetaX had no pushes in this window (11-02)

tilelang-metax last pushed on 10-26 and tilelang-musa on 09-30; neither repo had commits in this window’s 72 hours. This means this issue’s backend activity is concentrated on the Ascend, Hygon and mlir-ascend sides.

Source: https://github.com/tile-ai/tilelang-metax, https://github.com/tile-ai/tilelang-musa

III. Ecosystem and Adopters (TileOPs / TileFoundry / TileKernels / FlashQLA)

3.1 TileOPs: 15 merges in 72 hours, 13 landing on 11-01, nearly every one carrying a measured table and a manifest regression gate (11-01)

After the v0.1.0 release, TileOPs merged 13 PRs on 11-01 alone; together with #2794 on 10-30 and #2795 on 10-31, that makes 15 merges in 72 hours. The changes are almost all perf-class, covering attention, GEMM, elementwise, reduction, and MoE. Each one reports both busy and back-to-back timings on H200, or a comparison against vLLM and FlashInfer, and states that no already-measured row in the manifest regressed. This “merge with a table” pattern shows the operator library has entered a phase of per-shape, row-by-row calibration rather than feature fill-in.

Source: https://github.com/tile-ai/TileOPs/commits/main

3.2 TileOPs: GQA dense forward picks the decode or prefill program via a single measured rule, cutting selection regret from 1.818 to 1.017 (#2808)

Merged 11-01 13:04. GQADenseFwdOp and GQADenseWithLSEFwdOp now share a single rule, AttentionCall.dense_decode_program, to decide which program to run, taking as input query and key lengths, batch, head grouping, head dim, RoPE, and SM count: 2 to 64 query positions use a warp-specialized decode, packing each position within a KV head group into 64-row blocks; a single query position is split into 32 segments to fill one wave, or uses a batch-1 program with 1 to 2 KV heads per sequence. Selection regret relative to the fastest available program (geometric mean and maximum): single position improves from 1.068 and 1.87 to 1.018 and 1.69; 2 to 128 positions improves from 1.818 and 25.2 to 1.017 and 1.81. It also fixes two mainline bugs: the score scale multiplied by log2(e) vanishing under FP32, causing NaN or wrong values; and D256 multi-position calls failing to launch on SM90 due to insufficient shared memory.

Source: https://github.com/tile-ai/TileOPs/pull/2808

3.3 TileOPs: paged MHA decode extended to every head dim that fits in shared memory, GQA paged forward drops the old decode kernel (#2807 / #2797)

#2807 merged 11-01 12:30, extending paged MHA decode to every head dim provided one block’s shared memory can hold it; previously larger head dims simply skipped this path. #2797 merged the same day at 03:54, removing the old paged decode kernel from GQAPagedFwdOp and capping paged MHA decode at the head dims that can compile, effectively retracting the out-of-bounds capability left by the previous version. Together the two are a wrap-up of “extend capability first, then trim redundancy.”

Source: https://github.com/tile-ai/TileOPs/pull/2807, https://github.com/tile-ai/TileOPs/pull/2797

3.4 TileOPs: coop2 producer collapsed to a single warp, new 192-wide transposed block, W4A8 partial wave switched from stream-K to one CTA per tile (#2806 / #2805)

#2806 merged 11-01 12:02, collapsing the Hopper GEMM coop2 producer from multiple warps to a single load warp, and providing a uniform 192-wide transposed block when shared memory allows a three-stage pipeline; on H200, wgrad-q-b drops from 384.9 µs to 382.3 and mlp-up fp16 from 317.9 µs to 311.9 (back-to-back 458.5 to 449.6 and 369.0 to 367.3 respectively). The author states no measured GEMM row regressed; this is part of the #2791 goal, and dual-card confirmation is still pending. #2805 merged the same day at 10:36, changing the partial-wave W4A8 prefill grid that fills at least three-quarters of the SMs to one CTA per tile instead of stream-K; llama-8b-up-b33 drops from 23.52 µs to 17.98 (vLLM 20.42), b128 from 31.33 to 23.39 (vLLM 24.05), and across 44 N/K sweep groups for M 33 to 128 outside the manifest, the reshaped schedule is 5% to 36% faster, median 18%, with none slower.

Source: https://github.com/tile-ai/TileOPs/pull/2806, https://github.com/tile-ai/TileOPs/pull/2805

3.5 TileOPs: compile cache keyed by build target, operator layer uniformly checks output/input overlap (#2802 / #2801)

#2802 merged 11-01 11:31, fixing cross-device reuse of the compiled-program cache: both builder and Op entries are keyed by build target, lazy compilation and autotuning stay on the expected device, and acceptance covers 99 target-isolation, vendor, and grouped GEMM tests. #2801 merged the same day at 10:33, hoisting the “output must not share bytes with any other call tensor” check to the operator layer, with per-operator exceptions declared via the manifest’s overlaps field, removing four kernel-side checks including MoE unpermute, MoE grouped GEMM, and the persistent GEMM template; it also fixes a mainline race: IndexedExpertMLPFwdOp allowed out to overlap topk_weights, which was still being read by a reduction while being written. Host time for MoEPostPermuteFwdOp with out drops from 51.48 µs to 39.33.

Source: https://github.com/tile-ai/TileOPs/pull/2802, https://github.com/tile-ai/TileOPs/pull/2801

3.6 TileOPs bug in progress: four Norm operators lose precision on rows far from zero, overflow to NaN around 1e36 (#2812)

Opened 11-01. LayerNorm, AdaLayerNorm (including -Zero), GroupNorm, and BatchNorm currently sum the raw row directly in fp32 to compute mean and variance (BatchNorm uses E[x²] minus the squared mean), the same class of defect fixed for FusedAddLayerNorm in #2773 and being fixed for the InstanceNorm training kernel in #2811. Symptoms: an fp32 row of constant 10000.1 normalizes to roughly ±weight instead of bias, and a row of 10000 plus random values fails to match the float64 reference within fp32 tolerance; rows near 1e36 overflow the sum, producing all-NaN output in both fp32 and bf16. Affected paths span fragment, shared-memory walk, one-row-per-warp, tiled, and streaming implementations.

Source: https://github.com/tile-ai/TileOPs/issues/2812

3.7 TileFoundry: lowering consolidates issuing mesh and window splitting into one decision point, 83 scheduling fixtures byte-identical (#280 / #282)

#280 merged 10-31 00:47, consolidating the “what to emit per call” decision into one place; #282 merged 11-01 11:47, further consolidating “which mesh emits” and “how the window is split” into one place: analysis/emission.py gains copy_mesh, issue_owner, and issue_mesh, with copy_mesh and issue_owner sharing one helper so their only difference (how Partial is read) lives in a single place; three duplicated Slice splits are unified under a _cut helper. Acceptance is byte-level: of 83 scheduling fixtures, 75 finalize outputs match mainline exactly, and the remaining 8 fail on mainline as well; section 7.1 of docs/spec/passes.md writes this mesh decision into the spec.

Source: https://github.com/tile-ai/TileFoundry/pull/282, https://github.com/tile-ai/TileFoundry/pull/280

3.8 TileFoundry: site publishes v0.3 scheduling article “Scheduling, Designed for Agents” (#4 / #281)

The site repo merged #4 on 10-30, publishing the v0.3 article “Scheduling, Designed for Agents,” along with a directory structure for articles and figures, MathJax support for formulas, figure-caption and table styling, and per-figure anchors; the homepage Blog card now opens the blog index, which lists both articles; upstream-ref is unchanged and the site still renders v0.0.3. On the repo side, #281 announced the article in the README on 10-31. For the TileFoundry line, this is a step in moving “agent-oriented scheduling” from code and release notes into a public narrative.

Source: https://github.com/tile-ai/TileFoundry.github.io/pull/4, https://github.com/tile-ai/TileFoundry/pull/281

3.9 Adopter: FlashQLA merges SM120 Dual-CP forward and backward, compared against Inter-CP on 2 RTX 5090s for 32K to 128K sequences (#51)

Merged 10-30 03:02. The change adds Dual-CP forward and backward for SM120: forward reuses the existing state-scan kernel for card-level state aggregation, computing the ordered M product in 32-column blocks to stay within shared memory; backward propagates state in reverse order using the transposed M, reusing the M matrices cached during forward; it also fixes a shared-memory race in the backward kernel by synchronizing stage 7 with the dV store warp. Performance is measured on 2 RTX 5090s in BF16, chunk 32, sequence lengths 32K to 128K, against Inter-CP, with 3-run medians per case and 25 warmups plus 100 timed iterations per run.

Source: https://github.com/QwenLM/FlashQLA/pull/51

3.10 Adopter: TileKernels has had no pushes since 10-14 (11-02)

DeepSeek’s TileKernels last push was on 10-14, with no changes in this window. All effective adopter-side activity this period comes from Tongyi’s FlashQLA.

Source: https://github.com/deepseek-ai/TileKernels

IV. Community, Tutorials, and Events

4.1 RISC-V research chain takes shape: three repos convert Numba CUDA Python to TileLang, then lower restricted PrimFuncs to single-hart RVV C (10-31)

Community researcher zishu0131-png assembled three repos on the same day, 10-31: tilelang-riscv serves as the main entry point, describing the research goals, the two-stage compilation chain, and the version combinations; numba2tilelang handles static parsing of Numba CUDA Python and converts it to TileLang source; tilelang2rvv converts supported real tvm.tirx.PrimFunc into RVV intrinsic C, which is then compiled by Clang into an RV64GCV ELF and run on QEMU virt with a single hart. The author states the boundaries clearly: this is not an officially registered TileLang backend, nor a general GPU model simulator; threadIdx-dependent addressing, cross-hart synchronization, and unsupported IR are all rejected, blocks execute sequentially, and shared and fragment are mapped to single-hart local arrays. The research environment is TileLang 0.1.15, Clang 23.1.3, and QEMU 11.1.0, with no guarantee of compatibility with other versions, and it is explicitly noted that upstream thread-level artifacts cannot automatically be treated as acceptable input for this backend.

Source: https://github.com/zishu0131-png/tilelang-riscv

4.2 PTO-ISA/tilelangGym split from PTO-ISA/tilelang into its own repo, with the Ascend SimtVF path as the main regression gate (10-30)

This sensitivity and regression test suite was split out from examples/ascend/t_parallel_st_suite in PTO-ISA/tilelang, so that the test suite can independently pin the versions of TileLang and PTOAS. There are currently three main paths: Ascend SoftLib SimtVF (target=ascend, cython, the main regression gate, passing fully on the remat version), VectorizeParallelToPTO with VL’s vload/vstore, and hand-written SIMD DSL reference implementations using @pto.jit under benches; each test case directory contains a config.toml and VERDICT.md, plus weekly and CI regression scripts.

Source: https://github.com/PTO-ISA/tilelangGym

4.3 News side: no substantive hits within the window from Google News Chinese/English queries, Hacker News, or arXiv (11-02)

Three days of Google News Chinese and English queries returned no TileLang-related coverage falling within the window, and Hacker News and arXiv likewise had no new entries; all 20 items in the candidate list came from GitHub repository pushes, which are routine code activity rather than news. This issue’s information landscape therefore consists entirely of repository-side and community repos.

Source: https://news.google.com/

V. Trend Observations

The most noteworthy judgment in this window comes from upstream itself: it would rather roll back correctness improvements than keep ThreadSync’s complexity off the critical path. The rollback note spells out the cost—three classes of improvements (quotient guards, precise participating-thread bounds, and non-rectangular thread sets) are withdrawn together, keeping only the old conservative path, with #3732 deferred until after the TIRX migration is complete. A compiler project willing to publicly state “our prover budget is insufficient, so we are reverting to the conservative implementation” says more about the real constraints of the current stage than any number of added features: the TIRX migration is the top priority on the mainline, and all other optimizations must give way to it.

Echoing this are two Ascend-side documents on “converging toward the mainline”: the RFC in #1971 would replace the synchronization algorithm with the mainline core plus a standalone Z3 proof service—research first, replacement later, with an old TIR adaptation layer kept in between; #1975 directly migrates the entire Ascend repo to the mainline multi-backend architecture. Both paths incur migration costs, so near-term visible work skews toward foundational items: #1948 cuts the fixed host overhead per call from about 450 microseconds to about 106 microseconds, four documentation fact-checks, and CI cleanup of internal cache references are all this kind of work.

TileOPs, meanwhile, has shifted its rhythm from “releasing” to “tuning.” Of 15 merges in 72 hours, 13 landed on the same day, nearly every one accompanied by an H200 measured-results table and a “no manifest regression” statement, and it has begun using metrics such as selection regret to describe the quality of scheduling rules (#2808 from 1.818 to 1.017). This means the competitive focus for operator libraries has shifted from “does this operator exist” to “is the right program selected for every shape”—which is precisely where the long-term value of DSLs like TileLang relative to hand-written kernels lies.

Two new forks have appeared on the ecosystem side. One is hardware dialects: Hygon treats gfx948 as gfx946-compatible, while Ascend continues to fill in PTO documentation and symbolic shapes. The other is a language outlet: the RISC-V research chain lowers restricted PrimFuncs to single-hart RVV C—low star count, and the author explicitly states it is not an official backend, but it uses TileLang’s IR as a portable asset, the same kind of signal as the repo-level branch adaptations for Ascend and Hygon. With multiple forks existing simultaneously, whether the upstream TIRX migration can deliver a stable IR boundary will determine whether these downstream investments accumulate or get reworked.

Appendix: Sources and Verification Notes

Source Verification Table

Source Verification Result
tile-ai organization (29 repos) 10 repos pushed within the window
Main repo tilelang 7 merges to main; 4 new issues; 3 doc-site commits
TileOPs 15 merges to main (13 on 11-01); 3 new issues; 1 site commit
TileFoundry 3 merges; 1 site commit
tilelang-ascend 5 merges; 4 new issues (including daily test records and RFC)
tilelang-hygon 2 merges; 1 new PR under review
tilelang-mlir-ascend 1 merge; 1 new PR under review
tilelang-metax / tilelang-musa / TileRT / tilescale / DeepStack No pushes within the window
Release pages (tilelang / TileOPs / TileFoundry / tilelang-ascend / tilelang-hygon / mlir-ascend) No new versions within the window
FlashQLA 1 merge (#51)
TileKernels No pushes since 10-14
Three RISC-V research-chain repos / PTO-ISA/tilelangGym Pushes present; the three research-chain repos were created on the same day
Google News / Hacker News / arXiv No substantive hits within the window

Full Source List