Reporting period: Monday, September 14, 2026 to Sunday, September 20, 2026 — 7 calendar days, 5 daily-report publication days Sources: This publication’s daily RISC-V Global News Briefs (five weekday issues: 09-14, 09-15, 09-16, 09-17, 09-18); weekend developments on 09-19 and 09-20 were supplemented and reinforced through GitHub organization and key repository reviews Editorial note: This period covers five dimensions: standards and policy, instruction sets and open-source cores, operating systems and distributions, chips and hardware, and open-source community and industry activities. The five daily issues contain a total of 88 items (including each issue’s today’s highlights and verification records). This publication aggregates them by topic; all facts, version numbers, and dates come from verified sources in the relevant issues and from hands-on verification during this period.

1. This Week’s Highlights

  • SPMP, led by a Shanghai Jiao Tong University team, is officially merged into the RISC-V international instruction set standard — the first time a Chinese proposal has fully led an ISA feature (09-17): The privileged-state physical memory protection (SPMP) standard led by the IPADS team at Shanghai Jiao Tong University was reviewed and approved by the RISC-V International board of directors and formally written into the RISC-V instruction set architecture standard, making it the first ISA feature since the foundation’s inception to be initiated from scratch and fully led by a China-based team. The proposal replaces multi-level page tables with privileged-state physical memory isolation that “only checks the doorplate, not the index,” serving fixed-layout scenarios such as AI chips, automotive, and smart terminals with minimal hardware overhead; the project submitted its first design draft in September 2019 and completed standardization in nearly 2,500 days, and has already been deployed on XiangShan and Nuclei chip platforms. Source: Science and Technology Daily
  • The “15th Five-Year Plan” explicitly names advancing RISC-V R&D and industrialization, with policy signaling and capital moves converging in the same week (09-15): The Ministry of Industry and Information Technology and the National Development and Reform Commission jointly issued the “15th Five-Year Plan for the Development of the Electronic Information Manufacturing Industry,” which under the item “advancing software-hardware coordination” includes “advancing the R&D and industrialization of the fifth-generation reduced instruction set (RISC-V), supporting the application of RISC-V chips in fields such as artificial intelligence and embedded systems,” listed alongside “strengthening the adoption of domestic operating systems such as OpenHarmony.” In the same period, Nuclei completed its filing for listing guidance on the Beijing Stock Exchange (guidance agreement signed 09-08, filing completed 09-11); if all proceeds smoothly, it will become the first A-share listed company whose main business is RISC-V commercial CPU IP. Sources: Guandian, Beijing Business Today
  • SiFive and AMD demonstrate ROCm 10.0 running on a RISC-V data center platform, completing a three-stage “release—third-party analysis—capital markets” diffusion in three days (09-15 ~ 09-17): The demonstration used a BigSky SF-2U870 platform (32 P870-D cores, 2.0 GHz, 256 GB DDR5-5600, 4x PCIe Gen5 x16) as the head node, with a Radeon AI PRO R9700 GPU handling inference offload and running the Gemma 4 E2B model; from 09-16, third-party analysis raised the “neutral head node” discussion, noting that two GPU software stacks landed on the RISC-V host side within three weeks of the platform’s launch; on 09-17 the event reached financial channels such as Yahoo Finance, and AMD rose about 7% that day. AMD’s official wording was “an early step,” and the demonstration remains a validation system. Sources: SiFive, Futurum Group
  • Three automotive developments in one week: the first automotive RISC-V industry standard begins drafting, and DAMO Academy and Changan offer quantified automotive-grade assessments (09-16 ~ 09-17): At the Smart Vehicle Chip Ecosystem Conference, China Automotive Chip disclosed that the first RISC-V industry standard for the automotive sector (QC/T series) has begun drafting, with 34 domestic and international companies already participating; DAMO Academy’s Li Weili offered quantified experience — automotive-grade functional safety R&D cycles typically run 3 to 5 years, and there is a discrepancy of more than 5% (up to 7% to 10%) in STL diagnostic coverage between RTL and netlist simulation; Changan Automobile’s Ding Ke disclosed OEM assessment conclusions: RISC-V cores have surpassed ARM in MCU compute power, interrupt response can reach the entry function within 120 clock cycles, and the company is exploring an AI DSA architecture based on a custom instruction set. Sources: Phoenix Net (Wangtongshe), Gasgoo
  • The RISC-V Open Computing Forum was held in Beijing during the IC WORLD conference, with carrier benchmark platforms and mass-production server cases disclosed in parallel (09-18): The forum was hosted by the Beijing Integrated Circuit Society and the RDI Alliance, and organized by the Beijing RISC-V Digital Infrastructure Innovation Center. China Telecom Research Institute disclosed the “Beihai” RISC-V intelligent computing platform (a cluster of over a thousand cores, with a self-evolving agent framework) and pointed out three major bottlenecks: gaps in the software ecosystem, high adaptation costs, and a lack of large-scale cluster validation; Yuanshi Intelligent Computing introduced how the RISMA platform’s unified cross-architecture compute scheduling has been deployed in multiple data centers; Sophgo showcased two generations of mass-production server CPUs and deployment cases in intelligent computing centers and government clouds; the Beijing RDI Innovation Center proposed that next steps focus on building a validation and evaluation system for the intelligent computing foundation and laying out embodied-intelligence edge controllers. Sources: CCIDnet, Science and Technology Daily
  • A second case of “architectural route divergence” among domestic RISC-V chips: Suzhou Ruixin’s Gaoguang D35 mass production confirmed by the industrial park, and Aowei Lingxin’s RV9000 taped out and lit up (09-14 ~ 09-15): Ruixin’s “Gaoguang D35” achieved mass production with a “RISC-V plus dataflow architecture,” equipped with 128 GB of large video memory, anchored to edge-side physical AI, and announced it will launch a “Guangrong Community” for the dataflow architecture; the next day, Shenzhen Aowei Lingxin’s RV9000 series (RV9311 model) taped out and lit up, featuring a modular, configurable design of “RISC-V plus DSA (domain-specific architecture) plus NoC many-core,” with heterogeneous compute combinations of up to 24 cores. Both are based on vendor and industrial park statements, with no third-party independent testing corroboration yet. Sources: Suzhou Industrial Park Administrative Committee, Jiemian News
  • XiangShan advances twice in one week: vector floating-point units merged into a VFMac fused unit, a batch of 13 timing optimizations landed, and a new functional unit landed over the weekend (09-16 ~ 09-20): On 09-16, the complete data paths of VFALU, VFMul, and VFMac were merged, combining the original two vector floating-point functional units into a single VFMac, and fixing redundant mask write-back in floating-point comparison instructions; the same batch landed 13 timing optimizations covering critical paths in memory access and renaming. On the weekend of 09-20, the new FMUL FALUV2 functional unit, FltRegion, and a renaming free-list refactor landed, along with added support for a performance-triggered CI workload list; the accompanying simulation chain (GEM5 branch prediction moved to the second stage, NEMU and difftest timing alignment) advanced in parallel. Source: XiangShan commit history

II. Instruction Set and Architecture Ecosystem

Evolution Path After RVA23: Security, Matrix Extensions, and the “Development Options” Cadence

Jon Taylor of Canonical has systematically outlined the evolution direction after RVA23. On the security side, taking CFI as an example, this extension consists of two independent extensions, Zicfilp and Zicfiss, designed to defend against return-oriented and jump-oriented control flow attacks. The design strives to remain compatible with existing RVA23 hardware, leaving room for compiler toolchains to adapt first. For matrix extensions, three paths are given: VME reuses the standard vector state, requiring no OS changes; IME extends the vector register file and adds result registers; AME uses an entirely new register file. The latter two require the OS to be aware of the additional register state during context switches, and applications can probe at runtime via sys_riscv_hwprobe() to select an implementation path. RVA23.1 introduces “development options” such as Double Trap Handling and Supervisor Counter Delegation, adopting a cadence of first introducing them as development options and later mandating them in subsequent profiles, balancing software stability with the introduction of new features. Source: Ubuntu Official Blog (published 09-15, entered window 09-17)

XiangShan: From Vector Floating-Point Refactoring to Timing Convergence, Two Advancement Lines in One Week

  • Vector floating-point (new development work): On 09-16, the complete datapaths for VFALU, VFMul, and VFMac were merged, and the original two vector floating-point functional units were merged into a single VFMac fused unit, while also fixing the mask writeback of floating-point comparison instructions (avoiding disruption of subsequent computation sequences that depend on the mask); previously on 09-14, floating-point boxing was added for VMove results, and the timing for reversing vector source operands was moved to after register read. On the weekend of 09-20, the new FMUL FALUV2 functional unit and FltRegion structure were landed, and the rename free list was refactored from MEFreeList to StdFreeList. Author dates are concentrated between September 11 and 15, indicating new development work rather than a backlog merge.
  • Timing optimization batch (bulk wrap-up): A batch of 13 timing optimizations was merged in the same batch, covering critical paths such as page table walk second-level address generation, memory-side replay reason precomputation and load queue paths, unaligned forwarding, moving illegal issue checks forward to the S0 stage, vector store queue recovery and dequeue pipeline, and simplification of rename free list pre-allocation; author dates span August 31 to September 10, representing critical path convergence ahead of performance benchmarking.
  • Correctness polishing throughout the week: Fixes included correction of the useful counter mask derivation in the ITTAGE predictor, mispredicted branch training in IFU and FTQ for self-modifying code, exception PC propagation when exceptions and uncacheable accesses are triggered simultaneously, fixing CommonHR reads after s2_override, converging IFU exceptions to a single path of only fb(1); on 09-20 there were also fixes such as backend difftest VL now taking values from rename state.
  • ZhuJiang (L3 cache direction) enters the main repository: On 09-16, the XiangShan main repository integrated the ZhuJiang single-core topology (#6122); previously on 09-14, XSCache merged a one-time batch of 18 commits (ZhuJiang submodule parameterization, reset and build fixes, simulation environment adaptation, addition of the TestTopZhuJiang test top level, HN performance counters named by module path), and on 09-17 the Directory PSEL update timing was further fixed. The XiangShan memory system is evolving toward a “CoupledL2 plus independent L3” configuration, with the supporting simulation, reset, and performance collection chains being completed in sync. Source: XiangShan, XSCache

XiangShan Simulation and Verification Chain: NEMU, GEM5, and difftest Align Toward Real Hardware Timing

  • NEMU (reference model): 13 commits throughout the week. On the performance side: streamlined the riscv64 page table read path, cached MMU identity-mapped valid address state, delayed preparation of differential test CSR shadow copies, added inactive gating for basic-block profiling, and used memmove to accelerate GCC register export; on the correctness side: added scalar/vector store visibility checks and undefined tile region read detection for matrix extensions (AME) (#1224), restricted matrix load comparison to active regions, preserved RVH final TLB refill (#1218), and marked SHARE mode CSR dirty bits in differential testing.
  • GEM5 (XiangShan branch): cbo.zero now executes through the out-of-order core store buffer, added a pending interrupt delivery window after ROB drain, moved MBTB and TAGE branch prediction to the second pipeline stage, set vector memory access writeback to a 3-cycle latency, predecode alignment, L2 request source retention across buffers, Topdown statistics fixes, and late load cancellation exposure (#1163); starting 09-18, added weekly SPEC17 SMT and multi-core reference model calibration (#1162).
  • difftest (differential testing framework): Disabled Verilator’s SLP vectorization to avoid LLVM miscompilation contaminating verification results, adapted AME packed events to the NEMU ABI, and cleaned up residual prints from the elf loader. Observing the three together: XiangShan’s verification infrastructure is simultaneously doing two things—”running faster (NEMU optimization, CI container streamlining)” and “simulating more accurately (timing, visibility, interrupt semantics)”—representing normal convergence ahead of large-scale regression and performance benchmarking. Source: NEMU, GEM5, difftest

CORE-V Ecosystem: Concentrated Cleanup of Privilege Boundary and Floating-Point Correctness

  • CVW (Wally): Fixed PWM peripheral pending bit and register write issues and added self-checking tests; concentrated fixes for four consecutive IFU defects (satp-related, JALR least significant bit handling, flushm, bus fault); systematically cleaned up privilege register consistency under the “unsupported U mode” configuration (mcounteren illegal access, mstatus.MPP reset value illegal). Previously, the eight CVA6 commits on 09-13 also focused on privilege boundary conditions such as PMP, debug triggers, Zcmp, and xRET.
  • CVFPU: Fixed NaN boxing in the division and square root paths. UAP: Added BSC IP card support.
  • Consistent with XiangShan’s orientation during the same period: the open-source core community has generally entered a “correctness verification-driven” phase, where the pace of new features gives way to boundary condition convergence, and the advancement focus falls on security and privilege correctness—echoing the domestic security feature mainline represented by SPMP. Source: CVW, CVFPU, UAP

Compilers and Toolchains

  • LLVM XiangShan branch: Under the RV32 target, decomposed half-precision floating-point to 64-bit integer conversion into a two-step path via i32; added a “packed widening add-accumulate” vector builtin (corresponding to vector dot product and matrix multiply-accumulate scenarios, common primitives for AI inference and signal processing kernels).
  • DAMO XuanTie toolchain: Pushes appeared in the gcc and binutils-gdb repositories within the window, but after branch-by-branch verification there were no new commits on maintenance branches (gcc last stopped at the xuantie-gcc-14.3.0 branch from 09-13, same for binutils); pushes to the opensbi and zero_stage_boot repositories on the evening of 09-18 also showed no corresponding new commits on public branches upon re-inspection, all recorded as repository activity but not treated as version progress.
  • Academic side: Tampere University in Finland reported on researcher Kari Hepola’s work on customized compilation and design tools, aiming to make RISC-V processor design faster and easier, representing ecosystem basic research. Source: LLVM XiangShan branch

III. Operating Systems and Distributions

openRuyi: September release not yet out, SPECS package repository highly active all week

  • Dual-source verification across the official website and repository: the news page still shows the 2026.08 release (published 08-27) as the latest, and the 2026-09 release page continues to return not found. Given the monthly release cadence, the September release is expected late this month; at that point, focus on verifying toolchain versions, kernel versions, RVA23 integration, and updates to the cloud-native and AI software stacks.
  • On the repository side, spec files continued to be merged throughout the week (including the weekend): cloudpods and cloudpods-operator were added, Go was updated to 1.27.1, along with jemalloc 5.4.0, iptables 1.8.13, flashrom 1.8.0, assimp, glm, vkmark, and more; upstream addresses were updated for podman, buildah, and containers-common after migration, and riscv_hwprobe was allowed in the default seccomp configuration. Sources: openRuyi news page, openRuyi repository

revyos: Engineering the boot chain and kernel configuration for SG2044/K3 platforms

  • Kernel side (revyos/linux): UFS and display controller (DC) enabled for K3, K1 USB2 enabled for Banana Pi F3, SENSORS_LM63 temperature sensor enabled, and PICOHEART errata handling plus RESET_GPIO and other configurations merged in bulk; new LinuxBoot configuration and two CI pipelines (“cross-compilation plus native compilation”) were added, and the DRM_AST display driver was enabled (targeting server-grade display output scenarios).
  • Firmware side (firmware-sg204x, zsbl): CI added firmware variants for two SG2044 board types (SD3-10 and SD3-12), the device tree source was switched to the 7.3 kernel branch, and build targets were narrowed to EDK2 firmware only; ZSBL now loads the EDK2 device tree from a standard-named device tree file. The platform’s UEFI boot chain and firmware delivery process are being converged through engineering. Sources: revyos/linux, firmware-sg204x

deepin 25 RVA23 release completes adaptation for SpacemiT K3

  • On the RVA23 repository side, packaging enabled the GCC 16 toolchain with RVA23 support, and GCC 15 and binutils patches for SpacemiT’s IME vector extension were pushed to the next repository; on the image side, K3 device images were updated, platform kernel and bootloader source addresses were unified under the official organization, and the kernel build process now produces both U-Boot and ESOS components for K3; on the application side, llama.cpp and ggml completed all-architecture builds and verified GGUF model inference, with RVV vector acceleration confirmed effective on K3, running local models on 8 AI cores. End-side “distribution plus chip” joint adaptation continues to advance in small, rapid steps. Source: OSCHINA

Firmware and production toolchain: ZSBL, edk2-spacemit, and the K3 security stack

  • Sophgo’s ZSBL released SG2044 v3.1.0 on 09-17 (along with a rework of the versioning logic), followed by v3.2.0 on 09-18; within a week, sophon-tools advanced the unified build image to v1.2.0 (bundling a domestic GOPROXY and a Windows 7-oriented flashing toolchain), added f2fs partition format support for the OTA and backup paths, a filesystem guard for the recovery channel, a Chinese font fix in psewriter, and a “format TF card only” mode.
  • spacemit-com/edk2-spacemit released versions 0.0.8 and 0.0.9 (09-15 to 09-17): edk2 and edk2-platforms sources were vendored for in-tree builds, Debian packaging dependencies and K3 detection logic were completed; the K3 platform manifest added the optee_os repository on 09-18, bringing the security stack (OP-TEE) into the platform manifest. Sources: sophgo/zsbl, sophon-tools, edk2-spacemit

IV. Chips and Hardware

Data Center Platforms and IP Vendor Developments

  • SiFive BigSky SF-2U870: 32 P870-D cores, 2.0 GHz, 256 GB DDR5-5600, 4x PCIe Gen5 x16 (64 lanes total), 2x 7.68 TB U.2 SSDs, 10/25 Gb OCP NIC; the platform is now orderable. In a ROCm demo, the P870-D served as head node with the Radeon AI PRO R9700 handling inference offload; SiFive and AMD said they will continue evaluating larger models and more acceleration scenarios (see This Week’s Highlights for event details).
  • Industry retrospective on RISC-V cores embedded in NVIDIA GPUs: A long-form technical media piece traces NVIDIA’s use of RISC-V microcontrollers in GPUs since 2016, one of which has served as the GPU System Processor (GSP) since 2018, taking over a substantial portion of work previously handled by the graphics driver—enabling open-source drivers to achieve capabilities such as frequency control that were previously impossible. RISC-V shipments have long since entered mainstream compute chips at scale via embedded controllers. Source: XDA
  • Andes Technology: Announced it will host “Maximize RISC-V Performance with Custom Design” in Silicon Valley on October 7, spotlighting custom extension capabilities. Combined with its early-September move to bring the agentic AI design platform ChipAgents into its custom processor flow (cutting design time by roughly 30%), the competitive focus among IP vendors is shifting from core performance metrics to end-to-end delivery efficiency from design to verification. Source: Edge AI and Vision Alliance

Domestic Chips and IP

  • Nuclei: Holds the world’s first RISC-V automotive ASIL-D certification. In H1 2026, revenue was RMB 36.8745 million (up 41.09% YoY), overall gross margin 87.59%, R&D spending at 155.40% of revenue, and net loss attributable to parent widened by about 24.94% (losses narrowing period over period excluding share-based payment effects). Licensing customers and projects total more than 300; cash on hand is about RMB 485 million with zero debt. On the capital path, it has completed coaching registration with the Beijing Stock Exchange and plans to submit IPO application documents within 12 months of listing on the NEEQ. Source: Phoenix Finance
  • Architecture route divergence: Two non-general-purpose routes—Suzhou Ruixin’s “RISC-V plus dataflow” and Aowei Lingxin’s “RISC-V plus DSA plus NoC many-core”—saw volume production/bring-up progress in succession this week (see This Week’s Highlights for details). Both companies layer dedicated compute units on top of general-purpose CPUs and list networking and industrial scenarios as their first targets; neither disclosed quantitative performance or volume production timelines.

Automotive and Automotive-Grade

  • Infineon (Hot Chips 2026 recap): In automotive MCU scenarios, the attributes that truly decide victory are memory, connectivity, dedicated hardware, supply, and final BOM cost, while “whether there is an automotive-grade certified toolchain” determines who wins. Motor-control fast control loops require deadlines within 10 milliseconds and interrupt latency on the order of tens of nanoseconds. Infineon directly binds RISC-V to the zonal controller role, and its next-generation AURIX automotive MCU has been confirmed to take the RISC-V route. Source: ServeTheHome
  • On the launch of QC/T industry standard drafting, DAMO Academy’s automotive functional safety quantification experience, and Changan’s evaluation conclusions, see This Week’s Highlights. These three items correspond to the three levels of specification, methodology, and full-vehicle evaluation, jointly pointing to RISC-V on the domestic automotive side moving from point validation to systematic engineering.

Edge and Developer Hardware

  • JetKVM Mini (09-14): Powered by the ESP32-P4X (dual-core 400 MHz RISC-V) with a built-in hardware H.264 encoder, 32 MB PSRAM and 16 MB flash; wired version $39, wireless version $42 (the wireless version additionally uses an ESP32-C5 for Wi-Fi 6 and Zigbee/Thread). On sale October 26, with firmware open-sourced on day one. Combined with the previous window’s port of the OpenLara engine to the ESP32-P4, the same chip’s capability ceiling and cost floor are being pushed outward simultaneously. Source: CNX Software
  • Radxa Linkr v1.5.0 (09-18): Adds a plugin center (upload, install, start/stop, and uninstall), ZeroTier and EasyTier network plugins, adaptive screenshot watermarking, screenshot OCR (with offline recognition), experimental IPv6 support, and resolution and quality-switching control for the Agent API, plus improved keyboard compatibility and audio playback behavior. Source: linkr releases
  • Sipeed: The NanoKVM documentation system continues to be filled out (Go two-factor authentication, Cube flashing, power-on reboot troubleshooting, macOS reinstallation, model differentiation). The logic analyzer product line advanced twice in one week—the SLogic16U3 production flashing toolchain was refactored (unified DFU and APP mode flows, eFuse writing moved earlier, built-in libusb, shared flashing entry point for GUI and CLI), while the main SLogic repo built a shared device model and transport core from scratch, ported libsigrok drivers, split out Combo 8 model files, and rolled out CI across three platforms. LicheePi 4A mainline GPU stack documentation was also added. Source: SLogic, sipeed_wiki
  • Sophgo product-side adaptations: BM1684X2 was officially renamed CV84X6 with the DFSS MLIR wheel completed; LLM-TPU now supports text-only Qwen3.5 bmodel (no vision encoder dependency); sophon-demo ran all models in the FunASR_Nano speech recognition sample on the TPU and added real-time factor (RTF) and character error rate (CER) evaluation metrics.

Embodied Intelligence and Robotics

  • SpacemiT spacemit-robotics advanced on multiple fronts throughout the week: Engineering direction (MuJoCo simulation added headless mode moving toward CI, perception modules unified under code standards, IMU peripheral drivers built in full by default); humanoid motion control direction (support state and heartbeat policies, upper-body motion takeover, manual reference trajectory replay landed in the common library and Linglong, Unitree G1 dual-model support with constraint documentation, periodic motor position normalization, configurable speed bias for the ROS cmd_vel human-machine interface, ZMQ control and policy switching, voice control for standing motions); new SLAM line (ros2_orbslam3_run repo created on 09-20, supporting camera calibration read from CameraInfo and TF, with docs-ros publishing an ORB-SLAM3 usage guide and manifest synchronized inclusion). This stack has formed a three-stage landing path of “common library capabilities—model configuration—constraint documentation.”
  • Sophgo π0.5 VLA port (09-19): sophon-demo added a port of the π0.5 vision-language-action model on the BM1684X SoC, and in batch adapted 11 detection/tracking samples plus generative samples including FLUX.1, the StableDiffusion series, and ChatTTS to the CV84X6—edge-side large models and the robotics sample library are expanding in tandem. Source: sophon-demo
  • Kaihong M-Robots OS 3.0 Beta (released 08-28, picked up by media 09-13): The digital foundation explicitly supports four architectures—ARM, RISC-V, LoongArch, and x86—and is compatible with three major ecosystems: ROS, Dora-rs, and OpenHarmony, providing an upper-layer software entry point for RISC-V chips entering embodied intelligence systems. Source: Kaihong official site

V. Open-Source Community and Industry Events

Domestic Industry Events

  • RISC-V Open Compute Forum (Beijing, 09-18): The RDI Alliance made clear it will rely on the Beijing RDI Innovation Center to build four major platforms: scenario traction, ecosystem linkage, shared services, and collaborative governance. Intelligent computing and embodied intelligence edge devices were positioned as the two key battlegrounds for the next phase (see This Week’s Highlights for meeting takeaways).
  • IICIE International Integrated Circuit Innovation Expo (Shenzhen, concluded 09-09 to 09-11): Featured the “2026 RISC-V Industry Ecosystem Innovation Conference” and a RISC-V ecosystem application showcase area, with concentrated displays of open-source architecture flagship products such as the DAMO XuanTie chip series. The three exhibitions covered a total area of 320,000 square meters with more than 5,000 exhibiting companies. Source: China Daily Shenzhen
  • RISC-V and OpenHarmony Industrial IoT Salon (Shenzhen, 09-15): Hosted by the Shenzhen Internet of Things Industry Association, focusing on combining RISC-V chips with the open-source OpenHarmony operating system for industrial IoT scenarios, echoing the “open-source OpenHarmony plus RISC-V” phrasing in the 15th Five-Year Plan.
  • JLC Fourth Open-Source Hardware Spark Conference and Global AI Hardware Innovation Ecosystem Conference (Shenzhen, 09-19): The ECOS team displayed the world’s first fully open-source chip based on open-source EDA plus open-source IP plus open-source PDK (brought up in December 2025) in the exhibition area. The conference collected more than 400 projects cumulatively with over 2,200 innovators participating, covering embodied intelligence, key robotics hardware, AI edge computing, and intelligent terminals. Source: Shenzhen Municipal Government Portal

Community and International Collaboration

  • Jiachen Project student achievements: During a summer internship, Chen Hao, an undergraduate at Hefei University of Technology, landed one fix each in two upstream projects: llama.cpp (fixing garbled output from quantized models caused by the SpacemiT backend dispatch missing the Q5_0 branch) and LLVM (fixing clangd and clang-tidy crashes and adding regression tests). The validation platform was a SpacemiT K3 cloud instance. Source: Jiachen Project
  • UC Berkeley BAR group: Created a tutorial repository for IISWC 2026 titled “Building, Tracing, and Optimizing End-to-End Machine Learning and Robotics Workloads on Heterogeneous RISC-V SoCs,” using the lightweight Zephyr real-time runtime as the vehicle, reflecting academia’s assessment of the robotics real-time workload skill stack. Source: ucb-bar tutorial repo

VI. Trend Observations

  • China’s way of participating in RISC-V is shifting from “implementation and adaptation” to “definition and specification”: The merge of SPMP into the international instruction set standard marks the first time a domestic team has initiated and fully led an ISA feature from scratch; the launch of QC/T drafting pushes the automotive technology route into verifiable specification text; and the 15th Five-Year Plan completes the policy-level positioning. Standards, industry standards, and policy advancing on three fronts is a more structural change than any single product launch.
  • Competition on the data center route is shifting from “performance benchmarking” to “software stack delivery speed and ecosystem neutrality”: Two GPU software stacks landed on the RISC-V host side within three weeks of the BigSky platform’s launch; third-party analysis posed the question of a “neutral head node,” and the event spilled over into capital markets. Domestically, operators and vendors are beginning to provide large-scale validation data—China Telecom’s “Beihai” platform with a thousand-plus-core cluster, Yuanshi Zhisuan’s cross-architecture unified scheduling deployed across multiple data centers, and Sophgo’s two generations of production servers covering intelligent computing centers and government cloud. Three bottlenecks (software ecosystem gaps, high adaptation costs, and lack of large-scale cluster validation) remain the main constraints on this route.
  • Open-source high-performance cores are entering a “correctness deep-water zone plus performance convergence period”: XiangShan completed two advances this week—merging the vector floating-point unit (VFMac) and 13 timing optimizations—with the simulation chain continuously aligning to real hardware timing and memory models; CORE-V focused on cleaning up privilege-mode boundary conditions. Such work typically appears before tape-out or performance benchmarking, and the focus of both open-source cores falls on security and privilege correctness.
  • The capability ceiling and cost floor of edge-side RISC-V are being pushed outward simultaneously: A single ESP32-P4/P4X chip supports both 30 FPS software rendering and a $39 commercial IP-KVM; Sipeed refactored its logic analyzer flashing chain to be “mass-producible and traceable”; and the deepin RVA23 edition lets small-form-factor boards run large models locally. The edge is where RISC-V’s gap with desktop-class x86 and ARM is smallest and where scaled deployment is most likely.
  • Domestic vendors’ engineering mainline is clear: AI stack completion, volume delivery toolchain, and security stack advancing in parallel: SpacemiT continued strengthening the llama.cpp multimodal backend and the ORB-SLAM3 robotics chain; Sophgo prepared for downstream integration through ZSBL version iterations, CV84X6 adaptation, and the π0.5 VLA port; and the K3 platform list now includes OP-TEE, bringing the security stack into productization view.
  • The pure RISC-V IP licensing business model remains unproven, but the capitalization window has opened: Nuclei’s financial profile of “high growth, high gross margin, sustained losses, share-based payment dominated” provides a comparable sample. If the Beijing Stock Exchange coaching registration proceeds smoothly, RISC-V in China will move further from an open-source community narrative toward a business model that can be priced by capital markets.
  • What to watch next issue: Whether openRuyi 2026.09 is released on schedule (RVA23 plus cloud-native and AI stack updates); follow-up batches and performance data after XiangShan’s vector floating-point refactor; whether the DAMO XuanTie toolchain repository resumes substantive commits; the pace of Nuclei’s progress from coaching registration to formal filing; and SiFive and AMD’s ROCm validation progress on larger models and more acceleration scenarios.

Appendix: Sources and Fact-Checking

Sources (Five Daily Briefings)

  • 09-14 issue: window 09-11 08:18 to 09-14 08:18 (a three-day Monday window covering the previous weekend); entries from 09-11 to 09-13 (CVA6 commits, ESP32-P4 port of OpenLara, Infineon Hot Chips recap, etc.) are included as ongoing background, with original dates retained in the body.
  • 09-15 issue: window 09-14 08:18 to 09-15 08:18; 09-16 issue: 09-15 05:18 to 09-16 05:18; 09-17 issue: 09-16 05:18 to 09-17 05:18; 09-18 issue: 09-17 05:18 to 09-18 05:18.
  • No briefings on the weekend of 09-19 and 09-20 (weekend news is merged into Monday); developments in this cycle were included after review and reinforcement via GitHub organizations and key repositories.

Verification Methods

  • GitHub organization verification (168-hour window): covering 16 organizations and 10-plus key repositories, including DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT (including the robotics organization), Sipeed, revyos, OpenHW, Radxa Linkr, and openRuyi, with commit-level review and Atom feed fallback.
  • openRuyi dual-source verification: official website news page and release page status, plus GitHub repository commits.
  • Member company website inspection: 391 completed (234 unchanged, 89 with body changes, 68 failed to fetch); changes were mainly homepage marketing and section updates, with no substantive developments confirmed as new products, funding, or architecture releases; failed sites were mainly domestic and anti-scraping sites, which do not block the inspection.
  • Weekend commit review: commit-level verification of repositories including XiangShan, NEMU, GEM5, difftest, XSCache, spacemit-robotics, sipeed, sophgo, openRuyi, and radxa-linkr (via GitHub API and Atom feeds).

Notes on Terminology

  • The mass-production and energy-efficiency claims for Suzhou Ruixin’s “Gaoguang D35” and the tape-out information for Aowei Lingxin’s RV9000 are both vendor and park official statements, with no third-party independent test corroboration; the “15th Five-Year Plan” entry is planning language and does not constitute specific funding or project arrangements.
  • Large batch merges (several XSCache commits, revyos kernel configuration, etc.) are counted by merge time, with author dates noted in the body; the 09-18 pushes to the DAMO XuanTie opensbi and zero_stage_boot repositories were checked and found to have no corresponding new commits on public branches, so they are recorded as repository activity.
  • The three automotive items originated from a 09-16 meeting and entered the window via aggregation channels on 09-17; forum-type entries are annotated with their event dates; the original publication date of the Andes Technology event website was 09-11, and it is included as a 09-14 Chinese media reprint with a note.

Main References

Data sources: Daily RISC-V Global Developments Briefing (five issues from 2026-09-14 to 2026-09-18) and hands-on verification during this cycle; reporting period is 2026-09-14 to 2026-09-20.