Research window: 2026-11-04 05:00 ~ 2026-11-05 05:00 (Beijing time, 24 hours).

Sources: Google News aggregation (20+ query sets in Chinese and English, via proxy), Hacker News, Phoronix, CNX Software, LinuxGizmos, the openRuyi official news page and main repository, official website inspections of RISC-V International member companies (391 companies), riscv100.top leaderboard inspection, WeChat public accounts (Jiachen Project) and the RV-EAI official website, as well as commit and release searches across GitHub organizations and key repositories including XiangShan/NEMU/GEM5/XSCache, CORE-V CVW/CVA6, DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT and spacemit-robotics, Sipeed, revyos, openRuyi-Project, and Radxa Linkr.

This Issue’s Index

  • Today’s Highlights: Infineon releases its first RISC-V automotive-grade MCU platform AURIX RC1, up to 12 cores, ASIL D, sampling in H1 2027 (11-04)
  • Today’s Highlights: RISC-V Embodied AI Open Solution RV-EAI launched at the Wuzhen “Light of the Internet” event, jointly open-sourced by six organizations (11-04)
  • RISC-V 100 Leaderboard Updates
    • Site launches Run Comparison view, batch-generating item-by-item comparisons across three SPEC leaderboards for cross-architecture analysis (11-05 inspection)
  • I. Open Source Community and Software Ecosystem
    • XiangShan four fixes: ITTAGE no allocation by default, CBO commit type changed to STORE, ICache error messaging, SC switched to data-retention bypass (11-04)
    • NEMU two fixes: hvictl injected interrupt number preserved, zero-length vector loads marked dirty (11-04)
    • CORE-V cvw merges 15 commits: RV32IMCB configuration, latch-based register file, AMO bus atomics for HPTW (11-04/11-05)
    • openRuyi ten commits: Firefox 159, expat 2.10.0 security fix, CI switched to OBS signing keys (11-04)
    • felix86 fourteen commits: x86 compatibility layer adds signal and resource limits, recompiler adjusts code cache layout (11-04/11-05)
  • II. Product and Ecosystem Updates
    • Vietnam’s Viettel releases its first self-designed RISC-V security chip VGC v1.0 (released 11-03, reported 11-04)
    • Wireless Tag starts selling ESP32-P4X plus ESP32-C61 dual-chip dev board at $21 (11-04)
  • III. Deep Dive on Domestic Teams
    • C*Core CCRC4XXX automotive-grade AI MCU completes AUTOSAR and IAR toolchain adaptation (reported 11-04)
    • DAMO XuanTie’s ecosystem second half after 6 billion units shipped: summit content recapped by media (10-19 summit, reposted 11-04)
    • DAMO XuanTie privileged architecture test suite adds trap recovery and PMP cleanup (11-04)
    • Sophgo sophon-demo adapts Qwen3.5-0.8B, mcu hardens I2C broadcast and bus recovery (11-04)
    • SpacemiT model-zoo-vision unifies preprocessing geometry and mask rounding (11-04)
  • IV. Special Chapter on Embodied Intelligence and Robotics
    • RV-EAI site and repository status: site content is live, whitepaper and reference implementation directories remain placeholders (11-01)
    • ros2_humanoid adds RGBD SLAM and Nav2 navigation configuration for G1 (11-04)
    • humanoid_common’s policy_adapter supports SuperMimic history and reference inputs (11-04)
    • humanoid_unitree_g1 isolates planner CPU scheduling (11-04)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Source Verification Table

Today’s Focus: Infineon Unveils Its First RISC-V Automotive MCU Platform, AURIX RC1 — Up to 12 Cores, ASIL D, Sampling in H1 2027 (11-04)

On November 4 in Munich, Infineon announced the AURIX RC1, the company’s first MCU platform based on RISC-V and the first time the AURIX product line adopts an open instruction set. The company emphasized that it complements rather than replaces the existing MCU portfolio, and current TriCore series products will continue to ship. Positioning spans from traditional MCUs all the way to MCU/MPU hybrid devices, targeting software-defined vehicles (SDV), other software-defined systems (SDX), and physical AI.

On specifications, a single RC1 chip integrates up to 12 32-bit processing cores, a parallel processing unit for edge AI, and up to 40MB of embedded memory; Infineon also plans to introduce models within the same family that add 64-bit microprocessor capabilities, raising compute performance another notch. On the safety side, it supports up to ASIL D; cybersecurity meets ISO/SAE 21434 and the Cyber Resilience Act, with hardware-level physical protection and crypto agility, plus reserved support for post-quantum cryptography. On the communications side, it supports CAN XL, 10BASE-T1S, and multi-gigabit Ethernet, with some models integrating BRIGHTLANE Ethernet switching and hardware-accelerated data routing to reduce external components and main processor load.

The product logic is noteworthy: RC1 merges the previously separate AURIX and TRAVEO T2G lines into a single generation, using one shared RISC-V foundation to cover zone control, body, chassis, battery management, powertrain, ADAS safety management, and cockpit. RISC-V’s modularity lets Infineon tailor core counts and peripherals per application, while software, tools, and experience are reused across the same family — something past domain-by-domain point solutions could not achieve.

On the ecosystem side, it is paired with the DRIVECORE software stack, providing AUTOSAR, open-source software, functional safety, and cybersecurity support, including virtual prototypes (enabling development and validation before hardware is available) and AI-assisted migration tools to carry over existing AURIX and TRAVEO T2G projects. Infineon is a Premier Member of RISC-V International and a founding member of the joint venture Quintauris; the company says it is working with software, tools, middleware, and virtualization partners to build a common foundation for automotive-grade RISC-V.

Timeline: the family concept will be exhibited at electronica 2026 in Munich from November 10 to 13 (Hall C3, Booth 502), with samples targeted for H1 2027. Peter Schiefer, President of the Automotive Division, put it this way: “MCUs need to be more configurable, more scalable, and more adaptable, while maintaining the highest levels of safety and security.”

Placed in an industry context, this marks the first time a top-tier global automotive MCU vendor has switched its mainline product — not an experimental project — to RISC-V. Previously, automotive RISC-V was mostly driven by startups and domestic vendors (on the same day, Guoxin Technology’s CCRC4XXX completed AUTOSAR and IAR adaptation, see Chapter 3); Infineon’s entry means AUTOSAR stacks, functional safety certification, toolchains, and Tier 1 adaptation resources will follow this line. For domestic teams working on automotive RISC-V, this is both an ecosystem dividend (more mature toolchains and foundational software) and competitive pressure (an international giant using the same open instruction set to target the same market).

Date: 2026-11-04　Source: Infineon press release infpr202611-026

Today’s Highlight: RISC-V Embodied AI Open Solution RV-EAI Released at Wuzhen “Light of the Internet” Expo, Open-Sourced Jointly by Six Organizations (11-04)

On November 4, Wu Wei — RISC-V International Foundation ambassador, lead of the Jiachen Project, and co-founder of Kubuds — released the “RISC-V-based Embodied AI Open Solution” (RV-EAI) during the “Light of the Internet” Expo at the World Internet Conference Wuzhen Summit. The release carries the working codename “Qiyuan.” The solution was released jointly by the openKylin Embodied AI Working Group together with Milk-V, Chaorui Technology, Shanghai OpenLoong, SpacemiT, and Kubuds — six organizations in total — with all details evolving continuously as open-source projects on GitHub repositories and the official website. This year’s Wuzhen Summit runs from November 2 to 5; the “Light of the Internet” Expo opened first on November 2, and robotics and embodied AI sub-forums are held alongside it.

The solution’s thesis is to “publish interfaces, bills of materials, and reference implementations — not a fixed, finished machine.” It divides a robot into three layers by real-time requirement: the body layer runs microsecond-level current loops, covering joint motors, encoders, control boards, and wireless interconnect; the cerebellum layer runs millisecond-level control loops, with a real-time core running an RTOS and connecting to the joint bus via CAN-FD and EtherCAT; the cerebrum layer runs ten-millisecond-level inference, handling perception, planning, and VLA. All three layers are built on a single RISC-V instruction set architecture (RVA23, together with RVV, IME, AME, and VME), so replacing any one layer requires no rewrite of the other two. The key design of the cerebellum layer is that the real-time core and the AI core are physically isolated on the same chip and do not preempt each other, with the two domains coordinating via rpmsg, shared memory, and the bus.

The verifiable definition of “open” is given as five pluggable points: on the body side, RISC-V joint drivers and MCUs from Zhongke Benyuan, HPMicro, GigaDevice, WCH, Espressif, and others are available; on the cerebellum side, SpacemiT K3 / SoM260, Zhihe A210, and Chaorui’s and Milk-V’s UR-DP1000 / Titan; on the cerebrum compute side, K3, AXERA AX650N, and Rockchip RK1828; on the operating system layer, five distributions — openKylin, Debian, Ubuntu, Fedora, and openEuler — plus the RT-Thread real-time domain; on the framework and model layer, FlagOS, llama.cpp, TileLang, and vendor runtimes. The acceptance criteria are stated explicitly: replacing one point requires no changes to the other four, no re-adaptation of upper layers, and it must pass conformance tests.

The site also publishes the releasers’ self-measured data on a physical SpacemiT K3 machine (labeled “measured by this team,” Bianbu 4.0.7, kernel 6.18.3, collected October 21): 24.09 t/s for local inference of a 1B vision-language model, 12.00 t/s for a 24B MoE model, and 970 GMAC/s per core for IME2 (5632 GMAC/s across 8 threads), with an explicit note that vendor-claimed TOPS figures are peak values and not equal to usable throughput. Listing “vendor-published” and “measured by this team” separately is where this material exercises more restraint in data reporting than most solution documents — and it makes the claims checkable item by item.

The industry significance lies in consolidating capabilities already proven out in scattered fashion across China into one connectable set: on the chip side, a range of MCUs and AI CPUs genuinely based on RISC-V are available; on the system side, openKylin and RT-Thread provide dual-domain coordination; on the body side, OpenLoong’s full-size open-source humanoid robot serves as the validation environment. Previously, RISC-V adoption in embodied AI was mostly isolated case studies; what was missing was a public answer to the question “if I switch suppliers, do I have to redo the adaptation?” This solution turns that into a to-do list of interface specifications, a compatibility matrix, and conformance tests. The value of the next step depends not on the launch event, but on how many real machine models can ultimately be filled into the compatibility matrix.

Date: 2026-11-04　Source: Jiachen Project WeChat account: RISC-V-based Embodied AI Open Solution Released in Wuzhen, RV-EAI official website, kubuds/RV-EAI repository

RISC-V 100 Leaderboard Updates

This inspection round is judged to show significant changes (new What’s New entries and a batch of new cross-architecture leaderboard entries), so per our convention it is placed near the top of the main text.

New in What’s New: Run Comparison Now Available (marked New). The site has organized its existing cross-architecture records into an item-by-item comparison view, and comparison entries have accordingly appeared in bulk under the three cross-architecture leaderboards for SPEC CPU2006, SPEC CPU2017, and SPEC CPU2026 (a Benchmark summary row plus each sub-item). These entries carry no record date (the date column read by the script is “—”); they are a comparative presentation of existing results, not new benchmark runs from the day, and should not be read as architectural improvements.

Cross-architecture · SPEC CPU2006: Left is AWS EC2 Graviton5 (Neoverse V3) at 3.3GHz, right is XiangShan KMHv3 (da8dcb6a3) RTL at 3GHz, compared by per-GHz ratio. The three items where XiangShan leads are 462.libquantum (68.48 vs 127.10, right side 85.6% higher), 483.xalancbmk (35.76 vs 45.47, 27.2% higher), and 456.hmmer (19.45 vs 22.41, 15.2% higher); the nine items where it trails are concentrated in compilation and graph-search workloads: 403.gcc at 30.24 vs 20.74 (right side 31.4% lower), 473.astar 31.1% lower, 445.gobmk 26.8% lower, 464.h264ref 18.7% lower, 429.mcf 18.4% lower, 471.omnetpp 15.4% lower, 458.sjeng 15.7% lower, 400.perlbench 12.7% lower, and 401.bzip2 10.8% lower.

Cross-architecture · SPEC CPU2017: Left is AWS EC2 Graviton4 (Neoverse V2) at 2.8GHz, right is AMD Ryzen 9 9950X (Zen 5) at 5.7GHz. Graviton4 leads on 602.gcc_s (4.61 vs 3.60, right side 21.9% lower), 605.mcf_s (31.9% lower), 620.omnetpp_s (24.5% lower), 631.deepsjeng_s (27.1% lower), 641.leela_s (24.0% lower), and 657.xz_s (26.3% lower); Zen 5 wins only slightly on 648.exchange2_s (2.9% higher) and 623.xalancbmk_s (2.4% higher).

Cross-architecture · SPEC CPU2026: Left is AMD Ryzen 9 9950X (Zen 5) at 5.7GHz, right is DAMO XuanTie Yitian 710 (Neoverse N2) at 3GHz. Yitian 710 overtakes on 723.llvm_r (0.86 vs 0.96, right side 11.2% higher), 727.cppcheck_r (5.4% higher), 721.gcc_r (2.7% higher), 708.sqlite_r (2.3% higher), and 729.abc_r (1.0% higher); the largest gaps are 706.stockfish_r (2.31 vs 0.57, right side 75.1% lower), 750.sealcrypto_r (56.1% lower), 753.ns3_r (21.4% lower), 710.omnetpp_r (19.7% lower), and 714.cpython_r (14.7% lower).

Date: 2026-11-05 inspection　Sources: riscv100.top cross-architecture SPEC CPU2006, cross-architecture SPEC CPU2017, cross-architecture SPEC CPU2026, riscv100.top homepage

I. Open-Source Community and Software Ecosystem

XiangShan: Four Fixes — ITTAGE No Allocation by Default, CBO Commit Type Changed to STORE, ICache Error Messages, SC Switched to DataHoldBypass (11-04)

Four fixes were merged into the XiangShan main branch during the window. #6837 changes ITTAGE’s updateAlloc default from the don’t-care DontCare to false, preventing uninitialized branch history from being treated as “allocation allowed” and written into the prediction table; #6847 changes the commit type of CBO (cache block operation) instructions in the decode stage from the default to STORE—previously, if classified as load-type, they would take the wrong path in the memory queue and commit path; #6846 improves compile error messages for ICache and utility functions to make errors after generator expansion easier to locate; #6764 replaces the SC unit’s holdRead with DataHoldBypass, adjusting the read-data bypass path for store-conditional instructions. All four are convergence on timing and edge cases, with no architectural-level changes.

Date: 2026-11-04　Source: XiangShan commit log (kunminghu-v3)

NEMU: Two Fixes — Preserve Injected Interrupt Number in hvictl, Mark Zero-Length Vector Loads as Dirty (11-04)

Two fixes were merged into NEMU. #1279 fixes the loss of the injected interrupt number in vscause when hvictl injects an interrupt, ensuring the exception cause read by the guest matches the actual injection; #1278 marks zero-length vector loads as dirty—previously such instructions did not modify the destination register but could be treated as clean data by later optimizations relying on the dirty bit, reading stale values. Both fall in the combined scenario of virtualization and vector extensions.

Date: 2026-11-04　Source: NEMU commit log

CORE-V cvw: 15 Commits Merged — RV32IMCB Configuration, Latch-Based Register File, HPTW AMO Bus Atomics (11-04/11-05)

OpenHW’s CORE-V Wally core merged 15 commits during the window. #2045 advances the RV32IMCB configuration into the regression flow; #2050 changes the register file to a latch-based implementation, trading area and power for timing; #2046 routes HPTW AMO accesses through bus atomic transactions; #2052 fixes eBuFsmArb’s final-cycle handling; #2037 adjusts the synchronizer; #2007 adds trl5-rv32 coverage; #2048 introduces automatic ungroup in synthesis. There are also regression-script cleanups of the wfi lockstep exemption comment and dependency upgrades.

Date: 2026-11-04/2026-11-05　Source: CORE-V CVW commit log

openRuyi: Ten Commits — Firefox 159, expat 2.10.0 Security Fix, CI Switched to OBS Signing Key (11-04)

The ten commits in the openRuyi main repository during the window are mainly package version advances: Firefox upgraded to 159.0, expat upgraded to 2.10.0 with a security-fix tag, routine upgrades of python-aiobotocore 3.10.0 and python-nltk 3.10.4, and python-paste 3.11.0, python-multidict 7.2.1, and python-hydra-core 1.3.8 all tagged with security fixes. On the infrastructure side, apt-key in CI was replaced with a scoped OBS signing key, and a change to “run the update workflow with the openruyi container” was rolled back. The latest entries on the official news page remain the two from 2026-10 (10-19) and the distribution release from 2026-09 (09-30); no new version announcements during the window.

Date: 2026-11-04　Source: openRuyi main repository commit log, openRuyi official news page

felix86: Fourteen Commits — x86 Compatibility Layer Adds Signals and Resource Limits, Recompiler Adjusts Code Cache Layout (11-04/11-05)

felix86, a recompiler project that brings x86/x86-64 games to RISC-V Linux, made 14 commits during the window, focused on Linux compatibility layer correctness: signal delivery for PTRACE_SYSCALL, PTRACE_SETSIGMASK restoration, 32-bit setrlimit, returning EINVAL for invalid statfs64 lengths, the child thread tid pointer for fork clones, root-directory escape checks for creat and statfs, the extended mask for 32-bit signal frames, and an infinite loop for paths containing only slashes. On the recompiler side, it fixes the FSW C1 bit on x87 stack exceptions, moves the bad-address thunk before the code cache, and implements the TSO optimization for Volatile Metadata. The project released version 26.11 on November 2; this window is the post-release fix wave.

Date: 2026-11-04/2026-11-05　Source: felix86 commit log

II. Product and Ecosystem Updates

Vietnam’s Viettel Releases First Self-Designed RISC-V Security Chip VGC v1.0 (Announced 11-03, Reported 11-04)

On November 3 in Hanoi, the Vietnamese Government Cipher Committee and military electronics and telecommunications group Viettel released the country’s first self-designed secure semiconductor platform and its first chip, VGC v1.0. The chip uses the RISC-V architecture and a 28nm CMOS process, is packaged in a 10mm-square package, integrates approximately 300 million transistors, and hardwires Vietnam’s self-developed encryption algorithms into hardware, primarily targeting government and defense; official tests claim encryption and decryption speeds roughly 15 times those of pure software solutions for equivalent tasks. The chip has already been used in secure USB storage devices for government and defense agencies, with the next step being entry into the national digital signature certification system (which has issued more than 2 million digital certificates). The two parties also signed a cooperation agreement, planning to formulate a large-scale production plan and jointly develop a multi-core security chip platform integrating dedicated cryptographic components, with longer-term expansion into AI, 6G, smart cameras, drones, and robots. In related reporting, Reuters said Viettel’s first wafer fab, a $1.3 billion investment, may not be able to meet its target of trial production in 2027.

Date: 2026-11-03 (announcement) / 2026-11-04 (report)　Source: Guancha report, Chinese-language Saigon Giai Phong Daily

Wireless Tag Launches $21 ESP32-P4X + ESP32-C61 Dual-Chip Development Board (11-04)

Wireless Tag has launched the WT99P461-S1 full-featured development board, based on the 25×25mm WT01P461-S1 module: the main controller is the ESP32-P4X (ESP32-P4 v3.2), a dual-core RISC-V 360/400MHz chip with AI instruction extensions and a single-precision FPU, plus a low-power RISC-V core at up to 40MHz, paired with 32MB PSRAM and 16MB NOR; the wireless section is provided by the ESP32-C61 with 2.4GHz Wi-Fi 6 and Bluetooth 5.4. The board features 100M Ethernet, RS-485 and CAN terminals, MIPI DSI/CSI, microphone and 3W speaker interfaces, microSD, and dual USB OTG, and comes preloaded with a phone-like interface based on ESP-Brookesia and AI vision examples. The board alone is $21, and a kit with a 7-inch screen is $42.50.

Date: 2026-11-04　Source: CNX Software report

III. In-depth Coverage of Domestic Teams

CCRC4XXX Automotive AI MCU from Guoxin Technology Completes AUTOSAR and IAR Toolchain Adaptation (Reported 11-04)

Guoxin Technology’s CCRC4XXX series automotive AI MCU, based on a RISC-V multi-core architecture, has completed adaptation with Neusoft Reach’s NeuSAR CP platform and IAR Embedded Workbench for RISC-V. The three parties demonstrated this as a joint demo at the 6th RISC-V China Summit (October 18–20, Shenzhen). The chip is China’s first RISC-V multi-core post-quantum automotive AI MCU, built on a 22nm RRAM process, integrating a 0.3 TOPS NPU subsystem, with functional safety up to ASIL D and information security up to Evita-Full. It is compatible with both post-quantum and conventional cryptographic algorithms and supports NIST FIPS 203/204, relying on CGDMA for in-vehicle network data routing. Two variants have already been sampled: the CCRC4088S with 8+4 cores, 500MHz, and 14000DMIPS, targeting central domain control and intelligent driving; and the CCRC4046S with 4+4 cores, 500MHz, and 7000DMIPS, targeting body, BMS, and zonal domain control. Reach’s NeuSAR cCore complies with AUTOSAR R21-11/R23-11 and has obtained ASIL D certification, while IAR’s functional safety edition toolchain is certified by TÜV SÜD.

Date: 2026-11-04 (report)　Source: Sohu Tech report

The Second Half of the Ecosystem After XuanTie’s 6 Billion Units Shipped: Summit Content Revisited by Media (10-19 Summit, 11-04 Reprint)

On November 4, a media outlet published a retrospective article restating DAMO XuanTie’s disclosures at the 2026 RISC-V China Summit: XuanTie’s cumulative shipments have exceeded 6 billion units, and the C950 set a new record with 3.2GHz and a single-core SPECint2006 score exceeding 70; it holds a performance advantage of over 10% compared with the mainstream conventional-architecture processors it was benchmarked against across four categories of Agentic workloads, running Qwen3.8-Flash-Next at 43 tokens/s and DeepSeek V4-Flash at 38 tokens/s; underpinning these results are its in-house TPE matrix extension and co-optimization across memory, special functions, and software. On the ecosystem side, it disclosed that GCC optimization delivers over 10% typical performance improvement, deep Java adaptation on the C950 server achieves a 30% improvement, 128-core efficiency reaches approximately 78%, and 2,796 open-source test cases have been contributed to the RVI CSC certification baseline, with a cloud cluster of 20 A210 development boards carrying AOSP daily builds and CTS/VTS regression. Note: The article is primarily a reinterpretation of content from the October 18–20 summit rather than a new release on the day; the summit entry was already covered in a previous daily brief, so it is counted here as one media retrospective and not double-counted as release-type news.

Date: 2026-10-19 (summit disclosure) / 2026-11-04 (retrospective article)　Source: Zhihu column reprint

DAMO XuanTie Privileged Architecture Test Suite Fixes Trap Recovery and PMP Cleanup (11-04)

DAMO XuanTie made two commits within the window to its damo-rv-priv-ats repository on GitHub: one converted capability gating to declarative configuration, fixed the trap recovery path, and added optionally enabled checks; the other fixed an omission where PMP configuration was not cleared after switching from S-mode to HS-mode. The repository is a conformance test suite for the RISC-V privileged architecture (including the Hypervisor extension); it had previously introduced the T-SBI protocol layer, migrated each suite to the S-mode normative path, and integrated with the Sail model for instruction semantics comparison. Test suites of this kind are directly relevant to RVI’s certification baseline efforts.

Date: 2026-11-04　Source: damo-rv-priv-ats commit history

Sophgo sophon-demo Adapts Qwen3.5-0.8B; mcu Hardens I2C Broadcast and Bus Recovery (11-04)

Three Sophgo repositories received pushes within the window. sophon-demo added adaptation and stress-test data for Qwen3.5-0.8B on the CV84X6 (SE13-64) platform, continuing its cadence of validating each new model on successive SoC generations; the mcu repository’s HD12(v17) hardened debug I2C broadcast and added a recovery flow for I2C1 bus lockups; LLM-TPU had pushes but no new commits on the main branch within the window (the latest being the October 30 InternVL3 and Qwen3-ASR fixes), so it is not counted as an entry in this issue.

Date: 2026-11-04　Source: sophon-demo commit history, sophgo/mcu commit history

SpacemiT model-zoo-vision Unifies Preprocessing Geometry and Mask Rounding (11-04)

Two changes in SpacemiT’s vision model repository within the window: #115 refactored preprocessing to unify image scaling geometry calculations in one place, avoiding result discrepancies caused by different models each implementing their own; #114 fixed instance mask cropping for segmentation tasks, changing from truncation to rounding up to half-open interval pixel boundaries to prevent an edge row or column from being clipped. Meanwhile, pushes to ai-sdk and bianbu-agentic were submodule pointer updates with no substantive changes. Separately, Nuclei’s nuclei-tool-guide uniformly renamed the QEMU and VSCode extension release notes to changelog and completed the 2026.10 records, which is documentation housekeeping.

Date: 2026-11-04　Source: model-zoo-vision #115, #114, nuclei-tool-guide commit history

IV. Special Chapter on Embodied Intelligence and Robotics

RV-EAI Site and Repository Status: Site Content Is Live, Whitepaper and Reference Implementation Directories Still Placeholders (11-01)

The kubuds/RV-EAI repository referenced in the announcement was created on October 25 under the Apache-2.0 license, with its most recent push on November 1—meaning the site content was completed before the announcement. In the repository root, only website/ contains usable content (a Hugo site, bilingual in Chinese and English, with light and dark themes); the three directories whitepapers/, src/, and 3rd-party/ each currently contain only an explanatory README, whose status column reads “planned”: the whitepaper, reference implementation code, and third-party asset registry have yet to land.

This creates a timing gap with the announcement’s claim that “all reference code, reference images, and the compatibility list are open-sourced.” What can be verified at this stage is the architecture blueprint, the description of the interface list, and the data conventions on the site; code and images must wait for the repository to be further populated. For teams looking to integrate, what can be done immediately is to submit compatibility matrix entries according to the five pluggable points given on the site; for the parts requiring reference implementations, one must wait to see when the src/ directory turns from a placeholder into code.

This path does not start from zero. The three spacemit-robotics repositories from SpacemiT are doing precisely the integration of cerebellum-layer real-time performance with the cerebrum-layer navigation stack (the following three sections of this chapter) within this window; RV-EAI distills such scattered changes into common interfaces and a compatibility matrix—the two are two layers of the same thing: one is concrete landing commits on specific machine models, the other is a cross-vendor interface agreement.

Date: 2026-11-04 (announcement) / 2026-11-01 (most recent repository push)　Source: kubuds/RV-EAI repository, RV-EAI official website

ros2_humanoid Adds RGBD SLAM and Nav2 Navigation Configuration for G1 (11-04)

Two commits in the SpacemiT robotics line’s ros2_humanoid within the window: adding RGBD SLAM and Nav2 navigation configuration for the G1 humanoid robot, and hardware TF support for G1. The former wires visual-inertial localization and the navigation stack into G1’s startup flow; the latter completes the coordinate transform tree for the robot’s links and sensors—these two are prerequisites for taking G1 from “can walk” to “can move autonomously in unknown environments.”

Date: 2026-11-04　Source: ros2_humanoid commit history

humanoid_common’s policy_adapter Supports SuperMimic History and Reference Inputs (11-04)

Two commits in humanoid_common within the window: policy_adapter adds support for SuperMimic historical observations and reference inputs, enabling the policy adaptation layer to receive action references with temporal context; #28 isolates the asynchronous planner’s scheduling to prevent the planning thread and the motion control thread from dragging each other down. The same batch of fixes was synchronized to humanoid_unitree_g1 (#14 separates planner CPU scheduling), indicating that this scheduling model is sinking from the common layer down to specific machine-model repositories.

Date: 2026-11-04　Source: humanoid_common #28, humanoid_common commit history

humanoid_unitree_g1 Isolates Planner CPU Scheduling (11-04)

The Unitree G1 machine-model repository takes on the common layer’s scheduling fix, setting the planner thread’s CPU affinity and scheduling policy separately to avoid contending with the real-time control loop for the same core. This repository, together with humanoid_common and ros2_humanoid, forms a coherent set of changes within the window: the common layer defines interfaces and the scheduling model, while the machine-model repository implements the specific parameters.

Date: 2026-11-04　Source: humanoid_unitree_g1 #14

V. Summary and Trend Observations

  • The embodied intelligence side has its first cross-vendor pluggable common answer: What RV-EAI announced in Wuzhen is not a complete machine, but an interface list, a compatibility matrix, and an organizational approach for reference implementations, making the five points—body, cerebellum, cerebrum, operating system, and AI framework—into replaceable units, and providing an acceptance criterion of “swap one point without changing the other four.” Its quality is judged not by the launch event but by how many real machine models the compatibility matrix can ultimately include—the three commits in the SpacemiT robotics repositories this issue are exactly the kind of entries the matrix is meant to collect.
  • Two automotive-grade RISC-V items on the same day, different in nature but pointing to the same thing: Infineon moving its mainline AURIX product line to RISC-V is a route choice by a top-tier international vendor; Guoxin CCRC4XXX completing AUTOSAR and IAR adaptation is a domestic chip’s concrete step to fill out its software stack. Both show that the competitive focus in automotive-grade has shifted from “whether there is a RISC-V core” to “whether AUTOSAR, functional safety certification, and debugging tools can be in place simultaneously.”
  • Comparison data is more informative than total scores: The newly added Run Comparison on riscv100.top lays out item-by-item differences normalized per GHz—XiangShan KMHv3 leads Neoverse V3 on libquantum and xalancbmk, yet trails by 18% to 31% on compilation and graph-search workloads such as gcc, astar, and mcf; DAMO XuanTie Yitian 710 surpasses Zen 5’s per-GHz values on llvm, gcc, and sqlite, yet trails by 75% on stockfish. Such structural differences point to specific weaknesses in microarchitecture and compilers, and are more instructive for optimization than a single total score.
  • Open-source cores enter a period of incremental convergence: Four commits for XiangShan, two for NEMU, and fifteen for cvw, all boundary-condition and timing fixes with no architectural-level changes; cvw’s RV32IMCB configuration and latch-based register file represent progress in configuration coverage and physical implementation, indicating that the project’s focus is on making existing designs solid rather than adding new features.
  • The x86 compatibility layer enters polishing of edge cases: felix86’s 14 commits in a single window concentrate on long-tail issues such as signal semantics, 32-bit resource limits, statfs path validation, and x87 stack exceptions. The dense appearance of such commits usually means the main flow already runs, and what remains is to stop games and runtimes from occasional crashes.
  • The distribution side is relatively quiet: All ten commits in openRuyi within the window are package versions and security fixes, with no new release announcement on the official website; revyos’s main branch had no pushes within the window. The center of gravity of ecosystem activity this week is on the chip and automotive-grade side, not on distribution releases.

Appendix: Complete Source List

Complete Source List

Source Verification Table

Source Verification Result
Google News aggregation (20+ query sets in Chinese and English, 24-hour window) 5 substantive new items within the window: Infineon AURIX RC1 (multiple same-source reports merged into one), Vietnam VGC v1.0 security chip, C*Core automotive-grade RISC-V MCU ecosystem adaptation, XuanTie 6-billion-unit retrospective article, ESP32-P4X dev board; stock market pieces and SEO pieces on gambling and sports livestreams removed wholesale; zero hits within the window for queries on SiFive, SpacemiT, Espressif, RISC-V Summit, etc.
WeChat official account (Jiachen Project) 1 item within the window: RV-EAI solution published 11-04 22:24 (byline CNRV; a CNRV repost of the same text also exists); the six-party joint release, the release codename “Qiyuan”, three-tier real-time capability, five pluggable points, and five distributions plus RT-Thread all match the RV-EAI official site text item by item; the repository was created 10-25 with the latest push on 11-01, and the whitepapers / src / 3rd-party directories remain placeholders
GitHub organization checks (DAMO XuanTie, ESWIN, Sophgo, Nuclei, Espressif, SpacemiT, Sipeed, revyos, openHW, openRuyi, Radxa Linkr) Pushes within the window: Espressif 39 repos, SpacemiT 6 repos, Space Robotics 3 repos, Sophgo 3 repos, Sipeed 3 repos, CORE-V 3 repos, openRuyi 4 repos, XuanTie 1 repo, Nuclei 1 repo; zero pushes for ESWIN and Radxa Linkr
Commit checks on key repositories (XiangShan, XSCache, NEMU, difftest, GEM5, CORE-V, openRuyi, revyos) XiangShan 4 commits, NEMU 2 commits, cvw 15 commits, openRuyi 10 commits verified commit by commit; no commits within the window on the main branches of XSCache, GEM5, CVA6; zero pushes to the revyos main branch
RISC-V International member site inspection 391 sites inspected: 301 unchanged, 21 changed, 69 fetch failures; all 21 changes were homepage or event-page refreshes on university and consortium sites, with no substantive developments such as product, funding, or architecture announcements
riscv100.top inspection Notable change: “Run Comparison Now Available” added under What’s New, enabling batch generation of comparison entries across the SPEC CPU2006/2017/2026 leaderboards for different architectures; entries carry no record date and are a comparative presentation of existing results; the six RISC-V channel leaderboards and committee membership are unchanged
openRuyi official site news page Latest entries are the two from 2026-10 on ecosystem infrastructure and firmware (10-19) and the 2026-09 distribution release (09-30); no new version announcements within the window
Hacker News / Phoronix / CNX / LinuxGizmos HN surfaced the Infineon AURIX RC1 item (the source text is the official press release); CNX’s WT99P461-S1 already captured; Phoronix had only the NetBSD 11.1 release within the window, with no RISC-V content in the body, so not included
Summit official site change check The check window for this item (10-14 to 10-22) has passed; not performed this issue

Limitations

The news side is of moderate volume this issue, but the structural bias is pronounced: Chinese media coverage within the window was dominated by two automotive-grade stories (Infineon and C*Core), while the English side had essentially only the Infineon item, with the rest being reposts and commentary on the same press release, already merged into a single entry. The anonymous GitHub API did not hit rate limits within the window, and real-time data was obtained for all organizations and key repositories, but the zero-commit conclusions for repositories such as XSCache, GEM5, and CVA6 cover only the default branch; pushes to non-default branches were not examined one by one. The comparison entries on riscv100.top provide no record date; all figures in this article are quoted as displayed on the site, with no calculation performed, and their chronological relationship to historical results cannot be determined. The 69 member-site inspection failures are concentrated on domestic sites and pages requiring JavaScript rendering, including some domestic chip vendors, so product updates at the official-site level may have been missed. The factual basis for the RV-EAI item is the publisher’s own account plus the official website; specifications and measured figures are labeled per the publisher’s own methodology, and no third-party retest was performed this issue. The repository directory status is as measured this issue and will quickly become outdated as the repository is populated.